IVERILOG ?= iverilog
VVP      ?= vvp
YOSYS    ?= yosys
VERILATOR ?= verilator
RTL := rtl/pulse_counter.sv
TB  := tb/tb_pulse_counter.sv
BUILD := build

.PHONY: help sim lint synth all check-tools clean
help:
	@echo "Targets: sim lint synth all check-tools clean"

all: lint sim synth

$(BUILD):
	mkdir -p $(BUILD)

sim: | $(BUILD)
	$(IVERILOG) -g2012 -Wall -s tb_pulse_counter -o $(BUILD)/sim.vvp $(RTL) $(TB)
	cd $(BUILD) && $(VVP) sim.vvp | tee sim.log
	@grep -c "^PASS:" $(BUILD)/sim.log | grep -qx 1

lint:
	$(VERILATOR) --lint-only -Wall --top-module pulse_counter $(RTL)

synth: | $(BUILD)
	$(YOSYS) -Q -T -p 'read_verilog -sv $(RTL); hierarchy -check -top pulse_counter; proc; opt; check -assert; stat' > $(BUILD)/synth.log

check-tools:
	@bash scripts/check_tools.sh

clean:
	rm -rf $(BUILD)
