AI Accelerator Design - Architecture to Silicon

Course promise

This is the execution-focused AI accelerator design course for silicon teams. It teaches how to reason from workload symptoms to architecture mechanisms, then close decisions with reproducible evidence, ownership, and rollback-safe rollout criteria.

• Translate accelerator architecture concepts into measurable engineering decisions.

• Diagnose bottlenecks across dataflow, memory movement, scheduling, precision, and thermal limits.

• Connect architecture and runtime policy choices to product SLA and quality outcomes.

• Use one framework: workload -> mechanism -> artifact -> owner -> decision.

Course map

accelerator landscape and product fit
  -> dataflow architecture and array utilization
  -> systolic and tensor-core execution mechanics
  -> scheduling and mapping policy
  -> on-chip and off-chip memory strategy
  -> precision and power-thermal optimization
  -> verification, counters, and silicon bring-up

Related topics

• GPU Design course

• CPU Design course

• SoC Integration course

• Physical Design course

Section deep dive

Accelerator outcomes are cross-layer effects of mapping, memory behavior, and runtime policy.

Concept diagram

workload -> mapping -> memory and compute behavior -> SLA outcome

Metric graph

throughput / latency / perf-per-watt trend

Metrics and artifacts to collect

• throughput and latency profile

• power and thermal telemetry

• root-cause artifact packet

Mini case study

Freeze revisions and isolate first failing workload slice before optimization debate.

Debug branches

• Classify bottleneck

• Collect reproducible evidence

• Apply bounded fix

Senior review question

Ask: which first-principles bottleneck class explains the symptom, and what artifact proves it reproducibly?