NPU, GPU, and TPU Architectural Comparison: Expanded Case Study

Expanded case study

Expanded Case Study for NPU, GPU, and TPU Architectural Comparison is anchored on Tokens or inferences per second per watt at target model quality and batch profile.. Convert measurements into mechanism-backed decisions with clear owner accountability.

Use this page to rehearse incident closure: symptom intake, mechanism split, evidence request, owner assignment, bounded fix, and release decision.

Incident memo

ACCELERATOR REVIEW MEMO - AI Accelerator Landscape / NPU, GPU, and TPU Architectural Comparison

1. Symptom
   - Failing metric: Tokens or inferences per second per watt at target model quality and batch profile.
   - Workload or traffic slice: <name>
   - First failing layer or stage: <operator, schedule, memory, runtime>
   - Build and runtime tags: <compiler/firmware/runtime/hardware>

2. Mechanism hypothesis
   - Primary mechanism: GPUs prioritize programmability and broad parallel throughput with SIMT execution, large memory bandwidth, and mature software ecosystems. TPUs and TPU-like matrix engines push dense tensor throughput through systolic or matrix-multiply arrays, often with tightly coupled on-chip SRAM and deterministic dataflow scheduling. NPUs are a broader category that may combine scalar/vector cores, fixed-function units, and matrix engines optimized for edge or mobile constraints. The right comparison is not raw TOPS alone; it depends on kernel mix, sparsity support, precision modes, host-device orchestration overhead, and compiler maturity for the target model family.
   - Competing hypotheses: <dataflow mismatch, memory stalls, precision drift, thermal limits>
   - Missing evidence: <counter packet, trace, replay, signoff data>

3. Proposed action
   - Smallest reversible change: <mapping/runtime/policy/config>
   - Expected movement: <throughput, p99 latency, perf-per-watt>
   - Regression risk: correctness, quality, thermal, software compatibility

4. Signoff
   - Required artifact: Decision matrix mapping operator mix, precision needs, and deployment constraints to accelerator class.
   - Required owners: AI systems architect, accelerator microarchitecture lead, compiler and runtime owner, platform power-performance owner
   - Final decision: ship, bounded rollout, rollback, or escalate

AI accelerator deep dive

Accelerator selection quality depends on workload realism and full-stack delivery readiness.

Concept diagram

ACCELERATOR LANDSCAPE

model shape + SLA + power budget
  -> candidate platform shortlist
  -> benchmark under production-like load
  -> choose architecture + stack strategy

Metric graph

PLATFORM TRADE CURVE

throughput      ███████████
latency         ███████
energy          ████████
engineering risk █████

Metrics and artifacts to collect

• workload fit matrix

• latency-throughput sweep

• perf-per-watt dashboard

• owner and risk map

Mini case study

A platform looked best on synthetic GEMM but lost in production due to runtime overhead and memory-tail behavior.

Debug branches

• Validate workload representativeness

• Check software-stack maturity

• Tie KPI gains to product SLA

Senior review question

Ask: which first-principles bottleneck class explains the symptom, and what artifact proves it reproducibly?

Key takeaways

• Tie every accelerator claim to a reproducible workload slice and one primary metric trend.

• Prefer bounded fixes with clear owner and rollback boundary over broad tuning bundles.

Common pitfalls

• Optimizing synthetic kernels without production-shape validation.

• Reading average latency while ignoring p95 and p99 behavior.

• Declaring sparse or precision wins without fallback and quality evidence.

Principal accelerator review addendum

NPU, GPU, and TPU Architectural Comparison should be framed as a full-system behavior, not an isolated kernel trick. Production outcomes are set by model shape mix, compiler choices, runtime queueing policy, memory hierarchy limits, and silicon delivery margins.

GPUs prioritize programmability and broad parallel throughput with SIMT execution, large memory bandwidth, and mature software ecosystems. TPUs and TPU-like matrix engines push dense tensor throughput through systolic or matrix-multiply arrays, often with tightly coupled on-chip SRAM and deterministic dataflow scheduling. NPUs are a broader category that may combine scalar/vector cores, fixed-function units, and matrix engines optimized for edge or mobile constraints. The right comparison is not raw TOPS alone; it depends on kernel mix, sparsity support, precision modes, host-device orchestration overhead, and compiler maturity for the target model family. A useful explanation always ties observed symptom to a repeatable path where useful work was blocked, delayed, or diluted by overhead.

Use Tokens or inferences per second per watt at target model quality and batch profile. as an alarm, then anchor action using hard evidence such as Decision matrix mapping operator mix, precision needs, and deployment constraints to accelerator class..

Platform choice quality depends on workload realism, software maturity, and total-system economics. Senior reviews expect a chain of proof: workload intent -> mapping -> hardware behavior -> product impact.

Use this addendum to force explicit owner assignment, bounded fixes, and reproducible evidence before declaring closure.