NPU, GPU, and TPU Architectural Comparison: Interview Drills

Interview drills

Interview Drills for NPU, GPU, and TPU Architectural Comparison is anchored on Tokens or inferences per second per watt at target model quality and batch profile.. Convert measurements into mechanism-backed decisions with clear owner accountability.

PROMPT
You observe regression in Tokens or inferences per second per watt at target model quality and batch profile. for NPU, GPU, and TPU Architectural Comparison. Explain root cause and release decision.

STRONG ANSWER
1. Defines workload and first failing mechanism.
2. Explains mechanism: GPUs prioritize programmability and broad parallel throughput with SIMT execution, large memory bandwidth, and mature software ecosystems. TPUs and TPU-like matrix engines push dense tensor throughput through systolic or matrix-multiply arrays, often with tightly coupled on-chip SRAM and deterministic dataflow scheduling. NPUs are a broader category that may combine scalar/vector cores, fixed-function units, and matrix engines optimized for edge or mobile constraints. The right comparison is not raw TOPS alone; it depends on kernel mix, sparsity support, precision modes, host-device orchestration overhead, and compiler maturity for the target model family.
3. Requests proving artifact: Decision matrix mapping operator mix, precision needs, and deployment constraints to accelerator class.
4. Proposes bounded fix + owner + rollback-safe validation.

WEAK ANSWER
Gives generic optimization ideas without mechanism proof or ownership.

AI accelerator deep dive

Accelerator selection quality depends on workload realism and full-stack delivery readiness.

Concept diagram

ACCELERATOR LANDSCAPE

model shape + SLA + power budget
  -> candidate platform shortlist
  -> benchmark under production-like load
  -> choose architecture + stack strategy

Metric graph

PLATFORM TRADE CURVE

throughput      ███████████
latency         ███████
energy          ████████
engineering risk █████

Metrics and artifacts to collect

• workload fit matrix

• latency-throughput sweep

• perf-per-watt dashboard

• owner and risk map

Mini case study

A platform looked best on synthetic GEMM but lost in production due to runtime overhead and memory-tail behavior.

Debug branches

• Validate workload representativeness

• Check software-stack maturity

• Tie KPI gains to product SLA

Senior review question

Ask: which first-principles bottleneck class explains the symptom, and what artifact proves it reproducibly?

Key takeaways

• Tie every accelerator claim to a reproducible workload slice and one primary metric trend.

• Prefer bounded fixes with clear owner and rollback boundary over broad tuning bundles.

Common pitfalls

• Optimizing synthetic kernels without production-shape validation.

• Reading average latency while ignoring p95 and p99 behavior.

• Declaring sparse or precision wins without fallback and quality evidence.

Interview answer expansion

A strong answer on NPU, GPU, and TPU Architectural Comparison names the workload symptom, explains mechanism (GPUs prioritize programmability and broad parallel throughput with SIMT execution, large memory bandwidth, and mature software ecosystems. TPUs and TPU-like matrix engines push dense tensor throughput through systolic or matrix-multiply arrays, often with tightly coupled on-chip SRAM and deterministic dataflow scheduling. NPUs are a broader category that may combine scalar/vector cores, fixed-function units, and matrix engines optimized for edge or mobile constraints. The right comparison is not raw TOPS alone; it depends on kernel mix, sparsity support, precision modes, host-device orchestration overhead, and compiler maturity for the target model family.), and proposes one measurable validation plan.

Then it identifies owner and fallback action if the proposed fix under-delivers.

The goal is practical engineering reasoning, not keyword listing.