Workload Mapping Basics: Operators to Hardware: Expanded Case Study

Expanded case study

Expanded Case Study for Workload Mapping Basics: Operators to Hardware is anchored on Percent of model FLOPs sustained on hardware and memory-stall fraction by layer type.. Convert measurements into mechanism-backed decisions with clear owner accountability.

Use this page to rehearse incident closure: symptom intake, mechanism split, evidence request, owner assignment, bounded fix, and release decision.

Incident memo

ACCELERATOR REVIEW MEMO - AI Accelerator Landscape / Workload Mapping Basics: Operators to Hardware

1. Symptom
   - Failing metric: Percent of model FLOPs sustained on hardware and memory-stall fraction by layer type.
   - Workload or traffic slice: <name>
   - First failing layer or stage: <operator, schedule, memory, runtime>
   - Build and runtime tags: <compiler/firmware/runtime/hardware>

2. Mechanism hypothesis
   - Primary mechanism: Workload mapping converts a graph of operators into executable kernels that respect compute shape, memory hierarchy, and interconnect limits. Convolutions and GEMMs tend to map well to matrix engines when tiling aligns with local SRAM capacity, while attention, reductions, and control-heavy layers can expose synchronization or bandwidth bottlenecks. Effective mapping balances tile size, fusion boundaries, quantization format, and data-layout transforms so arithmetic units stay busy without overflowing memory traffic budgets. Compile-time scheduling plus runtime autotuning is usually required because the best plan varies with sequence length, batch size, and model variant.
   - Competing hypotheses: <dataflow mismatch, memory stalls, precision drift, thermal limits>
   - Missing evidence: <counter packet, trace, replay, signoff data>

3. Proposed action
   - Smallest reversible change: <mapping/runtime/policy/config>
   - Expected movement: <throughput, p99 latency, perf-per-watt>
   - Regression risk: correctness, quality, thermal, software compatibility

4. Signoff
   - Required artifact: Operator-to-kernel mapping sheet with tiling assumptions, fusion plan, and expected bottleneck class.
   - Required owners: ML compiler engineer, runtime systems engineer, performance modeling owner, framework integration lead
   - Final decision: ship, bounded rollout, rollback, or escalate

AI accelerator deep dive

Accelerator selection quality depends on workload realism and full-stack delivery readiness.

Concept diagram

ACCELERATOR LANDSCAPE

model shape + SLA + power budget
  -> candidate platform shortlist
  -> benchmark under production-like load
  -> choose architecture + stack strategy

Metric graph

PLATFORM TRADE CURVE

throughput      ███████████
latency         ███████
energy          ████████
engineering risk █████

Metrics and artifacts to collect

• workload fit matrix

• latency-throughput sweep

• perf-per-watt dashboard

• owner and risk map

Mini case study

A platform looked best on synthetic GEMM but lost in production due to runtime overhead and memory-tail behavior.

Debug branches

• Validate workload representativeness

• Check software-stack maturity

• Tie KPI gains to product SLA

Senior review question

Ask: which first-principles bottleneck class explains the symptom, and what artifact proves it reproducibly?

Key takeaways

• Tie every accelerator claim to a reproducible workload slice and one primary metric trend.

• Prefer bounded fixes with clear owner and rollback boundary over broad tuning bundles.

Common pitfalls

• Optimizing synthetic kernels without production-shape validation.

• Reading average latency while ignoring p95 and p99 behavior.

• Declaring sparse or precision wins without fallback and quality evidence.

Principal accelerator review addendum

Workload Mapping Basics: Operators to Hardware should be framed as a full-system behavior, not an isolated kernel trick. Production outcomes are set by model shape mix, compiler choices, runtime queueing policy, memory hierarchy limits, and silicon delivery margins.

Workload mapping converts a graph of operators into executable kernels that respect compute shape, memory hierarchy, and interconnect limits. Convolutions and GEMMs tend to map well to matrix engines when tiling aligns with local SRAM capacity, while attention, reductions, and control-heavy layers can expose synchronization or bandwidth bottlenecks. Effective mapping balances tile size, fusion boundaries, quantization format, and data-layout transforms so arithmetic units stay busy without overflowing memory traffic budgets. Compile-time scheduling plus runtime autotuning is usually required because the best plan varies with sequence length, batch size, and model variant. A useful explanation always ties observed symptom to a repeatable path where useful work was blocked, delayed, or diluted by overhead.

Use Percent of model FLOPs sustained on hardware and memory-stall fraction by layer type. as an alarm, then anchor action using hard evidence such as Operator-to-kernel mapping sheet with tiling assumptions, fusion plan, and expected bottleneck class..

Platform choice quality depends on workload realism, software maturity, and total-system economics. Senior reviews expect a chain of proof: workload intent -> mapping -> hardware behavior -> product impact.

Use this addendum to force explicit owner assignment, bounded fixes, and reproducible evidence before declaring closure.