Weight-Stationary Deep Dive

What this topic teaches

Weight-Stationary Deep Dive converts accelerator architecture concepts into release-ready engineering decisions. Weight-stationary dataflow pins filters or matrix fragments in PEs for many cycles while activations stream across compute lanes, reducing costly weight movement from SRAM or DRAM. It is often effective when model parameters are reused across many input windows or batched requests. The tradeoff is increased pressure on activation distribution and partial-sum routing networks, which can become limiting at larger mesh sizes. Effective implementations coordinate filter blocking, preload overlap, and activation tiling so stationary weights are not stranded by feeder stalls.

Senior-engineer framing question

When Off-array weight bandwidth per inference and achieved weight reuse across batch and sequence profiles. regresses, can you isolate the first failing execution mechanism, collect decisive evidence, assign owners, and close with rollback-safe validation?

ACCELERATOR EXECUTION FLOW - Weight-Stationary Deep Dive

request ingress and model metadata
      |
      v
graph lowering and kernel selection
      |
      v
tile/dataflow scheduling and memory placement
      |
      v
tensor execution + synchronization barriers
      |
      v
result assembly + quality/SLA validation
      |
      v
release decision and rollback guardrails

Evidence to collect

• Primary metric: Off-array weight bandwidth per inference and achieved weight reuse across batch and sequence profiles..

• Primary artifact: Reuse-and-bandwidth report mapping layer classes to weight residency and feeder utilization..

• Owners to include: accelerator architect, compiler mapping owner, SRAM subsystem owner, runtime scheduler owner.

• One reproducible failing workload and one stable comparator run.

• One fixed-metadata run with compiler/runtime/hardware tags locked.

Bandwidth lens

BANDWIDTH LENS - Weight-Stationary Deep Dive

working-set pressure
  ^
  |                saturation zone
  |          ----------------------------
  |      o   unstable tail latency
  |   o      tuning candidate
  | o        baseline behavior
  +-------------------------------------> optimization iteration

Primary metric tracked:
Off-array weight bandwidth per inference and achieved weight reuse across batch and sequence profiles.

Ownership layers

OWNERSHIP LAYERS - Weight-Stationary Deep Dive

+----------------------+--------------------------------+--------------------------------+
| Team                 | Primary responsibility         | Closure artifact               |
+----------------------+--------------------------------+--------------------------------+
| accelerator architect | mechanism and architecture intent| design rationale + tradeoffs   |
| compiler mapping owner | mapping, runtime, and execution   | profile traces + bottleneck map|
| SRAM subsystem owner | correctness, risk, and signoff    | test report + closure memo     |
+----------------------+--------------------------------+--------------------------------+

Key takeaways

• Start with mechanism classification before changing tuning knobs.

• Use one proving artifact for each major claim in review discussions.

• Close with explicit owners, validation matrix, and rollback criteria.

Common pitfalls

• Optimizing only peak throughput while p99 latency or quality regresses.

• Mixing evidence captured from mismatched runtime or thermal conditions.

• Declaring closure without production-like replay and guardrail checks.

AI accelerator deep dive

Dataflow choices are durable architecture decisions that shape memory and scheduling cost.

Concept diagram

DATAFLOW DECISION

input/output/weight stationary
  -> locality pattern
  -> movement cost
  -> throughput and power

Metric graph

DATAFLOW COST MIX

activation traffic   ███████
weight traffic       █████
partial-sum traffic  ██████

Metrics and artifacts to collect

• reuse factor map

• buffer pressure profile

• NoC traffic mix

• shape sensitivity analysis

Mini case study

A dataflow that won for convolution lost on attention-heavy batches due to activation movement pressure.

Debug branches

• Segment by model family

• Compare reuse vs movement

• Re-check mapping assumptions under batch variance

Senior review question

Ask: which first-principles bottleneck class explains the symptom, and what artifact proves it reproducibly?

Key takeaways

• Tie every accelerator claim to a reproducible workload slice and one primary metric trend.

• Prefer bounded fixes with clear owner and rollback boundary over broad tuning bundles.

Common pitfalls

• Optimizing synthetic kernels without production-shape validation.

• Reading average latency while ignoring p95 and p99 behavior.

• Declaring sparse or precision wins without fallback and quality evidence.