Weight-Stationary Deep Dive: Debug Playbook

Debug playbook

Debug Playbook for Weight-Stationary Deep Dive is anchored on Off-array weight bandwidth per inference and achieved weight reuse across batch and sequence profiles.. Convert measurements into mechanism-backed decisions with clear owner accountability.

1. Freeze workload seed, model revision, and execution environment.

2. Locate first persistent stage where metrics diverge.

3. Classify dominant mechanism: compute, memory, scheduling, precision, or thermal.

4. Build one focused reproducer and apply one bounded fix.

5. Re-run full correctness, quality, and performance matrix.

Review memo template

ACCELERATOR REVIEW MEMO - Dataflow Architectures / Weight-Stationary Deep Dive

1. Symptom
   - Failing metric: Off-array weight bandwidth per inference and achieved weight reuse across batch and sequence profiles.
   - Workload or traffic slice: <name>
   - First failing layer or stage: <operator, schedule, memory, runtime>
   - Build and runtime tags: <compiler/firmware/runtime/hardware>

2. Mechanism hypothesis
   - Primary mechanism: Weight-stationary dataflow pins filters or matrix fragments in PEs for many cycles while activations stream across compute lanes, reducing costly weight movement from SRAM or DRAM. It is often effective when model parameters are reused across many input windows or batched requests. The tradeoff is increased pressure on activation distribution and partial-sum routing networks, which can become limiting at larger mesh sizes. Effective implementations coordinate filter blocking, preload overlap, and activation tiling so stationary weights are not stranded by feeder stalls.
   - Competing hypotheses: <dataflow mismatch, memory stalls, precision drift, thermal limits>
   - Missing evidence: <counter packet, trace, replay, signoff data>

3. Proposed action
   - Smallest reversible change: <mapping/runtime/policy/config>
   - Expected movement: <throughput, p99 latency, perf-per-watt>
   - Regression risk: correctness, quality, thermal, software compatibility

4. Signoff
   - Required artifact: Reuse-and-bandwidth report mapping layer classes to weight residency and feeder utilization.
   - Required owners: accelerator architect, compiler mapping owner, SRAM subsystem owner, runtime scheduler owner
   - Final decision: ship, bounded rollout, rollback, or escalate

AI accelerator deep dive

Dataflow choices are durable architecture decisions that shape memory and scheduling cost.

Concept diagram

DATAFLOW DECISION

input/output/weight stationary
  -> locality pattern
  -> movement cost
  -> throughput and power

Metric graph

DATAFLOW COST MIX

activation traffic   ███████
weight traffic       █████
partial-sum traffic  ██████

Metrics and artifacts to collect

• reuse factor map

• buffer pressure profile

• NoC traffic mix

• shape sensitivity analysis

Mini case study

A dataflow that won for convolution lost on attention-heavy batches due to activation movement pressure.

Debug branches

• Segment by model family

• Compare reuse vs movement

• Re-check mapping assumptions under batch variance

Senior review question

Ask: which first-principles bottleneck class explains the symptom, and what artifact proves it reproducibly?

Key takeaways

• Tie every accelerator claim to a reproducible workload slice and one primary metric trend.

• Prefer bounded fixes with clear owner and rollback boundary over broad tuning bundles.

Common pitfalls

• Optimizing synthetic kernels without production-shape validation.

• Reading average latency while ignoring p95 and p99 behavior.

• Declaring sparse or precision wins without fallback and quality evidence.

Principal accelerator review addendum

Weight-Stationary Deep Dive should be framed as a full-system behavior, not an isolated kernel trick. Production outcomes are set by model shape mix, compiler choices, runtime queueing policy, memory hierarchy limits, and silicon delivery margins.

Weight-stationary dataflow pins filters or matrix fragments in PEs for many cycles while activations stream across compute lanes, reducing costly weight movement from SRAM or DRAM. It is often effective when model parameters are reused across many input windows or batched requests. The tradeoff is increased pressure on activation distribution and partial-sum routing networks, which can become limiting at larger mesh sizes. Effective implementations coordinate filter blocking, preload overlap, and activation tiling so stationary weights are not stranded by feeder stalls. A useful explanation always ties observed symptom to a repeatable path where useful work was blocked, delayed, or diluted by overhead.

Use Off-array weight bandwidth per inference and achieved weight reuse across batch and sequence profiles. as an alarm, then anchor action using hard evidence such as Reuse-and-bandwidth report mapping layer classes to weight residency and feeder utilization..

Dataflow selection governs reuse, movement cost, and predictability across model shapes. Senior reviews expect a chain of proof: workload intent -> mapping -> hardware behavior -> product impact.

Use this addendum to force explicit owner assignment, bounded fixes, and reproducible evidence before declaring closure.