NPU, GPU, and TPU Architectural Comparison - Interview Scenario

Scenario

You are reviewing NPU, GPU, and TPU Architectural Comparison under AI Accelerator Landscape.

OBSERVED METRIC
Tokens or inferences per second per watt at target model quality and batch profile.

45-MINUTE INTERVIEW FLOW
0-5: define workload and KPI
5-15: map first mechanism failure
15-25: identify proving artifact
25-35: propose bounded fix with owner
35-45: define validation matrix and rollback

Expected depth

• Mechanism to explain: GPUs prioritize programmability and broad parallel throughput with SIMT execution, large memory bandwidth, and mature software ecosystems. TPUs and TPU-like matrix engines push dense tensor throughput through systolic or matrix-multiply arrays, often with tightly coupled on-chip SRAM and deterministic dataflow scheduling. NPUs are a broader category that may combine scalar/vector cores, fixed-function units, and matrix engines optimized for edge or mobile constraints. The right comparison is not raw TOPS alone; it depends on kernel mix, sparsity support, precision modes, host-device orchestration overhead, and compiler maturity for the target model family.

• Artifact to request: Decision matrix mapping operator mix, precision needs, and deployment constraints to accelerator class.

• Owners to include: AI systems architect, accelerator microarchitecture lead, compiler and runtime owner, platform power-performance owner

AI accelerator deep dive

Accelerator outcomes are cross-layer effects of mapping, memory behavior, and runtime policy.

Concept diagram

workload -> mapping -> memory and compute behavior -> SLA outcome

Metric graph

throughput / latency / perf-per-watt trend

Metrics and artifacts to collect

• throughput and latency profile

• power and thermal telemetry

• root-cause artifact packet

Mini case study

Freeze revisions and isolate first failing workload slice before optimization debate.

Debug branches

• Classify bottleneck

• Collect reproducible evidence

• Apply bounded fix

Senior review question

Ask: which first-principles bottleneck class explains the symptom, and what artifact proves it reproducibly?

Key takeaways

• Tie every accelerator claim to a reproducible workload slice and one primary metric trend.

• Prefer bounded fixes with clear owner and rollback boundary over broad tuning bundles.

Common pitfalls

• Optimizing synthetic kernels without production-shape validation.

• Reading average latency while ignoring p95 and p99 behavior.

• Declaring sparse or precision wins without fallback and quality evidence.