On-Chip Memory Hierarchy

Section goal

How accelerator SRAM tiers, caching policy, HBM interface planning, and banking strategy determine realized throughput and latency under modern AI workloads.

How to study this section

1. Start with each topic hub and restate the mechanism in your own words.

2. Use reports and debug pages to separate symptoms from root causes.

3. Practice worked examples and interview drills under fixed metadata.

4. Close with checklist and silicon impact before making release claims.

Topics

1. sram-buffer-hierarchy/ - SRAM Buffer Hierarchy: Register File, Local SRAM, and Shared Buffers

2. scratchpad-vs-cache/ - Scratchpad vs Cache: Managed Locality Tradeoffs

3. hbm-bandwidth-planning/ - HBM Bandwidth Planning for Sustained Compute

4. memory-bank-conflicts/ - Memory Bank Conflicts: Detection and Mitigation

Related topics

• AI Accelerator course hub

AI accelerator deep dive

Memory hierarchy discipline sets the practical compute ceiling for AI accelerators.

Concept diagram

MEMORY HIERARCHY VIEW

register/SRAM -> shared buffers -> NoC -> HBM
  locality quality decides how long compute stays fed

Metric graph

MEMORY WALL SIGNALS

HBM near-saturation   ███████████
NoC backpressure      ███████
compute idle fraction █████

Metrics and artifacts to collect

• SRAM hit ratio

• HBM utilization timeline

• bank-conflict hotspots

• NoC queue pressure

Mini case study

HBM channels saturated under burst traffic while compute occupancy dropped, proving a memory-bound regime.

Debug branches

• Separate locality vs bandwidth limits

• Quantify bank conflicts

• Tune tiling before resizing compute arrays

Senior review question

Ask: which first-principles bottleneck class explains the symptom, and what artifact proves it reproducibly?