Scratchpad vs Cache: Managed Locality Tradeoffs

What this topic teaches

Scratchpad vs Cache: Managed Locality Tradeoffs converts accelerator architecture concepts into release-ready engineering decisions. Scratchpads expose explicit software control over placement, prefetch, and eviction, enabling predictable latency when access patterns are regular and compiler scheduling is mature. Hardware caches reduce software complexity and handle irregular reuse patterns automatically, but they can introduce nondeterministic misses and contention under multi-kernel interference. Most production systems blend both: critical tiles are pinned or staged through scratchpads while less predictable data uses cache paths. The choice should be based on measured reuse distance, synchronization pattern, and development cost, not ideology.

Senior-engineer framing question

When Delivered throughput change and miss or spill overhead when moving a kernel between cache-managed and scratchpad-managed execution. regresses, can you isolate the first failing execution mechanism, collect decisive evidence, assign owners, and close with rollback-safe validation?

ACCELERATOR EXECUTION FLOW - Scratchpad vs Cache: Managed Locality Tradeoffs

request ingress and model metadata
      |
      v
graph lowering and kernel selection
      |
      v
tile/dataflow scheduling and memory placement
      |
      v
tensor execution + synchronization barriers
      |
      v
result assembly + quality/SLA validation
      |
      v
release decision and rollback guardrails

Evidence to collect

• Primary metric: Delivered throughput change and miss or spill overhead when moving a kernel between cache-managed and scratchpad-managed execution..

• Primary artifact: Kernel locality decision matrix comparing cache and scratchpad policy by operator class..

• Owners to include: compiler/runtime architect, kernel performance engineer, hardware cache designer, serving systems owner.

• One reproducible failing workload and one stable comparator run.

• One fixed-metadata run with compiler/runtime/hardware tags locked.

Bandwidth lens

BANDWIDTH LENS - Scratchpad vs Cache: Managed Locality Tradeoffs

working-set pressure
  ^
  |                saturation zone
  |          ----------------------------
  |      o   unstable tail latency
  |   o      tuning candidate
  | o        baseline behavior
  +-------------------------------------> optimization iteration

Primary metric tracked:
Delivered throughput change and miss or spill overhead when moving a kernel between cache-managed and scratchpad-managed execution.

Ownership layers

OWNERSHIP LAYERS - Scratchpad vs Cache: Managed Locality Tradeoffs

+----------------------+--------------------------------+--------------------------------+
| Team                 | Primary responsibility         | Closure artifact               |
+----------------------+--------------------------------+--------------------------------+
| compiler/runtime architect | mechanism and architecture intent| design rationale + tradeoffs   |
| kernel performance engineer | mapping, runtime, and execution   | profile traces + bottleneck map|
| hardware cache designer | correctness, risk, and signoff    | test report + closure memo     |
+----------------------+--------------------------------+--------------------------------+

Key takeaways

• Start with mechanism classification before changing tuning knobs.

• Use one proving artifact for each major claim in review discussions.

• Close with explicit owners, validation matrix, and rollback criteria.

Common pitfalls

• Optimizing only peak throughput while p99 latency or quality regresses.

• Mixing evidence captured from mismatched runtime or thermal conditions.

• Declaring closure without production-like replay and guardrail checks.

AI accelerator deep dive

Memory hierarchy discipline sets the practical compute ceiling for AI accelerators.

Concept diagram

MEMORY HIERARCHY VIEW

register/SRAM -> shared buffers -> NoC -> HBM
  locality quality decides how long compute stays fed

Metric graph

MEMORY WALL SIGNALS

HBM near-saturation   ███████████
NoC backpressure      ███████
compute idle fraction █████

Metrics and artifacts to collect

• SRAM hit ratio

• HBM utilization timeline

• bank-conflict hotspots

• NoC queue pressure

Mini case study

HBM channels saturated under burst traffic while compute occupancy dropped, proving a memory-bound regime.

Debug branches

• Separate locality vs bandwidth limits

• Quantify bank conflicts

• Tune tiling before resizing compute arrays

Senior review question

Ask: which first-principles bottleneck class explains the symptom, and what artifact proves it reproducibly?

Key takeaways

• Tie every accelerator claim to a reproducible workload slice and one primary metric trend.

• Prefer bounded fixes with clear owner and rollback boundary over broad tuning bundles.

Common pitfalls

• Optimizing synthetic kernels without production-shape validation.

• Reading average latency while ignoring p95 and p99 behavior.

• Declaring sparse or precision wins without fallback and quality evidence.