Scratchpad vs Cache: Managed Locality Tradeoffs: Debug Playbook

Debug playbook

Debug Playbook for Scratchpad vs Cache: Managed Locality Tradeoffs is anchored on Delivered throughput change and miss or spill overhead when moving a kernel between cache-managed and scratchpad-managed execution.. Convert measurements into mechanism-backed decisions with clear owner accountability.

1. Freeze workload seed, model revision, and execution environment.

2. Locate first persistent stage where metrics diverge.

3. Classify dominant mechanism: compute, memory, scheduling, precision, or thermal.

4. Build one focused reproducer and apply one bounded fix.

5. Re-run full correctness, quality, and performance matrix.

Review memo template

ACCELERATOR REVIEW MEMO - On-Chip Memory Hierarchy / Scratchpad vs Cache: Managed Locality Tradeoffs

1. Symptom
   - Failing metric: Delivered throughput change and miss or spill overhead when moving a kernel between cache-managed and scratchpad-managed execution.
   - Workload or traffic slice: <name>
   - First failing layer or stage: <operator, schedule, memory, runtime>
   - Build and runtime tags: <compiler/firmware/runtime/hardware>

2. Mechanism hypothesis
   - Primary mechanism: Scratchpads expose explicit software control over placement, prefetch, and eviction, enabling predictable latency when access patterns are regular and compiler scheduling is mature. Hardware caches reduce software complexity and handle irregular reuse patterns automatically, but they can introduce nondeterministic misses and contention under multi-kernel interference. Most production systems blend both: critical tiles are pinned or staged through scratchpads while less predictable data uses cache paths. The choice should be based on measured reuse distance, synchronization pattern, and development cost, not ideology.
   - Competing hypotheses: <dataflow mismatch, memory stalls, precision drift, thermal limits>
   - Missing evidence: <counter packet, trace, replay, signoff data>

3. Proposed action
   - Smallest reversible change: <mapping/runtime/policy/config>
   - Expected movement: <throughput, p99 latency, perf-per-watt>
   - Regression risk: correctness, quality, thermal, software compatibility

4. Signoff
   - Required artifact: Kernel locality decision matrix comparing cache and scratchpad policy by operator class.
   - Required owners: compiler/runtime architect, kernel performance engineer, hardware cache designer, serving systems owner
   - Final decision: ship, bounded rollout, rollback, or escalate

AI accelerator deep dive

Memory hierarchy discipline sets the practical compute ceiling for AI accelerators.

Concept diagram

MEMORY HIERARCHY VIEW

register/SRAM -> shared buffers -> NoC -> HBM
  locality quality decides how long compute stays fed

Metric graph

MEMORY WALL SIGNALS

HBM near-saturation   ███████████
NoC backpressure      ███████
compute idle fraction █████

Metrics and artifacts to collect

• SRAM hit ratio

• HBM utilization timeline

• bank-conflict hotspots

• NoC queue pressure

Mini case study

HBM channels saturated under burst traffic while compute occupancy dropped, proving a memory-bound regime.

Debug branches

• Separate locality vs bandwidth limits

• Quantify bank conflicts

• Tune tiling before resizing compute arrays

Senior review question

Ask: which first-principles bottleneck class explains the symptom, and what artifact proves it reproducibly?

Key takeaways

• Tie every accelerator claim to a reproducible workload slice and one primary metric trend.

• Prefer bounded fixes with clear owner and rollback boundary over broad tuning bundles.

Common pitfalls

• Optimizing synthetic kernels without production-shape validation.

• Reading average latency while ignoring p95 and p99 behavior.

• Declaring sparse or precision wins without fallback and quality evidence.

Principal accelerator review addendum

Scratchpad vs Cache: Managed Locality Tradeoffs should be framed as a full-system behavior, not an isolated kernel trick. Production outcomes are set by model shape mix, compiler choices, runtime queueing policy, memory hierarchy limits, and silicon delivery margins.

Scratchpads expose explicit software control over placement, prefetch, and eviction, enabling predictable latency when access patterns are regular and compiler scheduling is mature. Hardware caches reduce software complexity and handle irregular reuse patterns automatically, but they can introduce nondeterministic misses and contention under multi-kernel interference. Most production systems blend both: critical tiles are pinned or staged through scratchpads while less predictable data uses cache paths. The choice should be based on measured reuse distance, synchronization pattern, and development cost, not ideology. A useful explanation always ties observed symptom to a repeatable path where useful work was blocked, delayed, or diluted by overhead.

Use Delivered throughput change and miss or spill overhead when moving a kernel between cache-managed and scratchpad-managed execution. as an alarm, then anchor action using hard evidence such as Kernel locality decision matrix comparing cache and scratchpad policy by operator class..

Memory hierarchy quality determines whether compute remains fed or sits idle behind bandwidth walls. Senior reviews expect a chain of proof: workload intent -> mapping -> hardware behavior -> product impact.

Use this addendum to force explicit owner assignment, bounded fixes, and reproducible evidence before declaring closure.