AI Accelerator Design · All levels
Scratchpad vs Cache: Managed Locality Tradeoffs: Worked Example
Worked Example for Scratchpad vs Cache: Managed Locality Tradeoffs.
Worked example
Worked Example for Scratchpad vs Cache: Managed Locality Tradeoffs is anchored on Delivered throughput change and miss or spill overhead when moving a kernel between cache-managed and scratchpad-managed execution.. Convert measurements into mechanism-backed decisions with clear owner accountability.
A regression appears in Delivered throughput change and miss or spill overhead when moving a kernel between cache-managed and scratchpad-managed execution.. Strong closure isolates first failing stage, proves mechanism, applies one reversible fix, and validates blast radius before release.
Execution lens
ACCELERATOR EXECUTION FLOW - Scratchpad vs Cache: Managed Locality Tradeoffs
request ingress and model metadata
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v
graph lowering and kernel selection
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v
tile/dataflow scheduling and memory placement
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v
tensor execution + synchronization barriers
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v
result assembly + quality/SLA validation
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v
release decision and rollback guardrailsDecision matrix
EVIDENCE MATRIX - Scratchpad vs Cache: Managed Locality Tradeoffs
+-----------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence | Tells you | Does not prove | Next action |
+-----------------------------+--------------------------------+--------------------------------+---------------------------+
| occupancy + timeline traces | where utilization is lost | precise root cause | map to memory and schedule|
| cache/SRAM/bandwidth stats | data movement pressure | model-level quality impact | correlate with quality run|
| counter + profile alignment | bottleneck class confidence | rollout safety | run full regression matrix|
| thermal/power telemetry | sustained operating envelope | correctness closure | pair with verification |
| before/after scenario pack | mitigation movement | long-tail stability | execute guardrail replay |
+-----------------------------+--------------------------------+--------------------------------+---------------------------+AI accelerator deep dive
Memory hierarchy discipline sets the practical compute ceiling for AI accelerators.
Concept diagram
MEMORY HIERARCHY VIEW
register/SRAM -> shared buffers -> NoC -> HBM
locality quality decides how long compute stays fedMetric graph
MEMORY WALL SIGNALS
HBM near-saturation ███████████
NoC backpressure ███████
compute idle fraction █████Metrics and artifacts to collect
SRAM hit ratio
HBM utilization timeline
bank-conflict hotspots
NoC queue pressure
Mini case study
HBM channels saturated under burst traffic while compute occupancy dropped, proving a memory-bound regime.
Debug branches
Separate locality vs bandwidth limits
Quantify bank conflicts
Tune tiling before resizing compute arrays
Senior review question
Ask: which first-principles bottleneck class explains the symptom, and what artifact proves it reproducibly?
Key takeaways
Tie every accelerator claim to a reproducible workload slice and one primary metric trend.
Prefer bounded fixes with clear owner and rollback boundary over broad tuning bundles.
Common pitfalls
Optimizing synthetic kernels without production-shape validation.
Reading average latency while ignoring p95 and p99 behavior.
Declaring sparse or precision wins without fallback and quality evidence.
Worked-example reasoning
Suppose Delivered throughput change and miss or spill overhead when moving a kernel between cache-managed and scratchpad-managed execution. regresses only under burst traffic. The shallow response is clock scaling. The stronger response is to inspect queueing, mapping, and memory-pressure interactions first.
If occupancy drops with high memory stalls, prioritize locality and scheduling fixes. If occupancy remains high with latency spikes, inspect contention and fairness policy.
Pick one bounded change per hypothesis and validate against baseline artifacts.