Operator Fusion and Tiling: Interview Drills

Interview drills

Interview Drills for Operator Fusion and Tiling is anchored on Kernel launch overhead reduction and on-chip reuse ratio for representative model blocks.. Convert measurements into mechanism-backed decisions with clear owner accountability.

PROMPT
You observe regression in Kernel launch overhead reduction and on-chip reuse ratio for representative model blocks. for Operator Fusion and Tiling. Explain root cause and release decision.

STRONG ANSWER
1. Defines workload and first failing mechanism.
2. Explains mechanism: Fusion combines adjacent graph operators into fewer kernels so intermediate tensors can stay in registers or local SRAM instead of round-tripping through global memory. Tiling then partitions fused workloads into shapes that fit accelerator buffers and maximize data reuse while preserving vector or matrix engine alignment. The best fusion boundary is workload-dependent: too little fusion leaves bandwidth and launch overhead on the table, while too much fusion can increase register pressure, spill traffic, and compilation complexity. Effective mapping uses profile-driven boundaries and tile shapes that balance compute occupancy with memory-system limits.
3. Requests proving artifact: Fusion and tile-plan worksheet linking operator groups, tile shapes, and expected bottleneck shifts.
4. Proposes bounded fix + owner + rollback-safe validation.

WEAK ANSWER
Gives generic optimization ideas without mechanism proof or ownership.

AI accelerator deep dive

Scheduling quality decides whether architecture headroom reaches product throughput.

Concept diagram

SCHEDULING PIPELINE

compile plan -> runtime queue -> core placement -> completion and tail behavior

Metric graph

TAIL-LATENCY DRIVERS

queueing delay      ███████
core imbalance      █████
mapping fallback    ████

Metrics and artifacts to collect

• queue wait profile

• batch policy impact

• core-level fairness

• operator fusion effect

Mini case study

Aggressive fusion reduced launch overhead but increased memory bursts that worsened p95 latency.

Debug branches

• Inspect tail first, not average

• Check fairness across streams

• Validate fusion against memory constraints

Senior review question

Ask: which first-principles bottleneck class explains the symptom, and what artifact proves it reproducibly?

Key takeaways

• Tie every accelerator claim to a reproducible workload slice and one primary metric trend.

• Prefer bounded fixes with clear owner and rollback boundary over broad tuning bundles.

Common pitfalls

• Optimizing synthetic kernels without production-shape validation.

• Reading average latency while ignoring p95 and p99 behavior.

• Declaring sparse or precision wins without fallback and quality evidence.

Interview answer expansion

A strong answer on Operator Fusion and Tiling names the workload symptom, explains mechanism (Fusion combines adjacent graph operators into fewer kernels so intermediate tensors can stay in registers or local SRAM instead of round-tripping through global memory. Tiling then partitions fused workloads into shapes that fit accelerator buffers and maximize data reuse while preserving vector or matrix engine alignment. The best fusion boundary is workload-dependent: too little fusion leaves bandwidth and launch overhead on the table, while too much fusion can increase register pressure, spill traffic, and compilation complexity. Effective mapping uses profile-driven boundaries and tile shapes that balance compute occupancy with memory-system limits.), and proposes one measurable validation plan.

Then it identifies owner and fallback action if the proposed fix under-delivers.

The goal is practical engineering reasoning, not keyword listing.