AI Accelerator Design · All levels

Systolic Arrays

Mesh-based matrix engines, stationary dataflows, tiling strategies, and utilization constraints that determine throughput, energy efficiency, and scaling behavior.

Section goal

Mesh-based matrix engines, stationary dataflows, tiling strategies, and utilization constraints that determine throughput, energy efficiency, and scaling behavior.

How to study this section

Start with each topic hub and restate the mechanism in your own words.
Use reports and debug pages to separate symptoms from root causes.
Practice worked examples and interview drills under fixed metadata.
Close with checklist and silicon impact before making release claims.

Topics

systolic-mesh-basics/ - Systolic Mesh Basics
weight-stationary-dataflow/ - Weight-Stationary Dataflow
output-stationary-dataflow/ - Output-Stationary Dataflow
array-scaling-utilization/ - Array Scaling and Utilization

AI accelerator deep dive

Systolic efficiency is governed by feed quality, tile fit, and bubble control.

Concept diagram

diagram

SYSTOLIC WAVEFLOW

operand stream -> wavefront launch -> PE mesh compute -> reduction/writeback
                         ^ bubbles and feed stalls reduce realized throughput

Metric graph

diagram

UTILIZATION LOSSES

tile mismatch      ███████
feed stalls        █████████
sync bubbles       █████

Metrics and artifacts to collect

mesh occupancy timeline
fill-drain overhead
tile mismatch histogram
DRAM stall attribution

Mini case study

Increasing mesh size did not help until scheduling and tile alignment removed persistent wavefront bubbles.

Debug branches

Measure bubble source first
Classify compute vs memory starvation
Tune tile policy before frequency changes

Senior review question

Ask: which first-principles bottleneck class explains the symptom, and what artifact proves it reproducibly?

Practice this lesson

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