Array Scaling and Utilization

What this topic teaches

Array Scaling and Utilization converts accelerator architecture concepts into release-ready engineering decisions. Larger arrays raise theoretical peak throughput, but realized gains depend on feeding operands fast enough and keeping tiles well matched to mesh dimensions. As the mesh grows, edge effects, padding overhead, and load imbalance can leave significant fractions of PEs idle for small or irregular layer shapes. Memory hierarchy limits often dominate: if SRAM banking, NoC bandwidth, or DRAM service cannot scale with compute, utilization drops despite additional silicon area. Senior architecture work therefore couples array sizing with workload distribution analysis, tiling strategy, and roofline-style bottleneck modeling before committing to a larger mesh.

Senior-engineer framing question

When Realized utilization, TOPS/W, and latency scaling as array dimensions increase under fixed memory system constraints. regresses, can you isolate the first failing execution mechanism, collect decisive evidence, assign owners, and close with rollback-safe validation?

ACCELERATOR EXECUTION FLOW - Array Scaling and Utilization

request ingress and model metadata
      |
      v
graph lowering and kernel selection
      |
      v
tile/dataflow scheduling and memory placement
      |
      v
tensor execution + synchronization barriers
      |
      v
result assembly + quality/SLA validation
      |
      v
release decision and rollback guardrails

Evidence to collect

• Primary metric: Realized utilization, TOPS/W, and latency scaling as array dimensions increase under fixed memory system constraints..

• Primary artifact: Scaling study pack with roofline plots, shape-wise utilization histograms, and bottleneck attribution..

• Owners to include: accelerator architect, system architect, memory subsystem owner, compiler/runtime owner, capacity planning owner.

• One reproducible failing workload and one stable comparator run.

• One fixed-metadata run with compiler/runtime/hardware tags locked.

Bandwidth lens

BANDWIDTH LENS - Array Scaling and Utilization

working-set pressure
  ^
  |                saturation zone
  |          ----------------------------
  |      o   unstable tail latency
  |   o      tuning candidate
  | o        baseline behavior
  +-------------------------------------> optimization iteration

Primary metric tracked:
Realized utilization, TOPS/W, and latency scaling as array dimensions increase under fixed memory system constraints.

Ownership layers

OWNERSHIP LAYERS - Array Scaling and Utilization

+----------------------+--------------------------------+--------------------------------+
| Team                 | Primary responsibility         | Closure artifact               |
+----------------------+--------------------------------+--------------------------------+
| accelerator architect | mechanism and architecture intent| design rationale + tradeoffs   |
| system architect | mapping, runtime, and execution   | profile traces + bottleneck map|
| memory subsystem owner | correctness, risk, and signoff    | test report + closure memo     |
+----------------------+--------------------------------+--------------------------------+

Key takeaways

• Start with mechanism classification before changing tuning knobs.

• Use one proving artifact for each major claim in review discussions.

• Close with explicit owners, validation matrix, and rollback criteria.

Common pitfalls

• Optimizing only peak throughput while p99 latency or quality regresses.

• Mixing evidence captured from mismatched runtime or thermal conditions.

• Declaring closure without production-like replay and guardrail checks.

AI accelerator deep dive

Systolic efficiency is governed by feed quality, tile fit, and bubble control.

Concept diagram

SYSTOLIC WAVEFLOW

operand stream -> wavefront launch -> PE mesh compute -> reduction/writeback
                         ^ bubbles and feed stalls reduce realized throughput

Metric graph

UTILIZATION LOSSES

tile mismatch      ███████
feed stalls        █████████
sync bubbles       █████

Metrics and artifacts to collect

• mesh occupancy timeline

• fill-drain overhead

• tile mismatch histogram

• DRAM stall attribution

Mini case study

Increasing mesh size did not help until scheduling and tile alignment removed persistent wavefront bubbles.

Debug branches

• Measure bubble source first

• Classify compute vs memory starvation

• Tune tile policy before frequency changes

Senior review question

Ask: which first-principles bottleneck class explains the symptom, and what artifact proves it reproducibly?

Key takeaways

• Tie every accelerator claim to a reproducible workload slice and one primary metric trend.

• Prefer bounded fixes with clear owner and rollback boundary over broad tuning bundles.

Common pitfalls

• Optimizing synthetic kernels without production-shape validation.

• Reading average latency while ignoring p95 and p99 behavior.

• Declaring sparse or precision wins without fallback and quality evidence.