Systolic Mesh Basics: Debug Playbook

Debug playbook

Debug Playbook for Systolic Mesh Basics is anchored on Sustained MAC utilization versus theoretical peak under target GEMM shapes and memory-feed constraints.. Convert measurements into mechanism-backed decisions with clear owner accountability.

1. Freeze workload seed, model revision, and execution environment.

2. Locate first persistent stage where metrics diverge.

3. Classify dominant mechanism: compute, memory, scheduling, precision, or thermal.

4. Build one focused reproducer and apply one bounded fix.

5. Re-run full correctness, quality, and performance matrix.

Review memo template

ACCELERATOR REVIEW MEMO - Systolic Arrays / Systolic Mesh Basics

1. Symptom
   - Failing metric: Sustained MAC utilization versus theoretical peak under target GEMM shapes and memory-feed constraints.
   - Workload or traffic slice: <name>
   - First failing layer or stage: <operator, schedule, memory, runtime>
   - Build and runtime tags: <compiler/firmware/runtime/hardware>

2. Mechanism hypothesis
   - Primary mechanism: A systolic array spatially maps multiply-accumulate work onto a grid of processing elements (PEs) where activations and weights move rhythmically between neighbors. Instead of repeatedly fetching operands from global memory, data is reused as it flows across rows and columns, while partial sums propagate along deterministic paths. This regular communication pattern simplifies timing closure, routing, and control relative to highly dynamic fabrics, but requires careful launch scheduling so wavefronts arrive in lockstep. Practical performance therefore depends on matching tile dimensions, operand streaming cadence, and pipeline latency balancing across the mesh.
   - Competing hypotheses: <dataflow mismatch, memory stalls, precision drift, thermal limits>
   - Missing evidence: <counter packet, trace, replay, signoff data>

3. Proposed action
   - Smallest reversible change: <mapping/runtime/policy/config>
   - Expected movement: <throughput, p99 latency, perf-per-watt>
   - Regression risk: correctness, quality, thermal, software compatibility

4. Signoff
   - Required artifact: Wavefront timing worksheet with PE occupancy trace and per-tile feed/drain schedule.
   - Required owners: accelerator architect, microarchitecture owner, compiler mapping owner, performance modeling owner, physical design owner
   - Final decision: ship, bounded rollout, rollback, or escalate

AI accelerator deep dive

Systolic efficiency is governed by feed quality, tile fit, and bubble control.

Concept diagram

SYSTOLIC WAVEFLOW

operand stream -> wavefront launch -> PE mesh compute -> reduction/writeback
                         ^ bubbles and feed stalls reduce realized throughput

Metric graph

UTILIZATION LOSSES

tile mismatch      ███████
feed stalls        █████████
sync bubbles       █████

Metrics and artifacts to collect

• mesh occupancy timeline

• fill-drain overhead

• tile mismatch histogram

• DRAM stall attribution

Mini case study

Increasing mesh size did not help until scheduling and tile alignment removed persistent wavefront bubbles.

Debug branches

• Measure bubble source first

• Classify compute vs memory starvation

• Tune tile policy before frequency changes

Senior review question

Ask: which first-principles bottleneck class explains the symptom, and what artifact proves it reproducibly?

Key takeaways

• Tie every accelerator claim to a reproducible workload slice and one primary metric trend.

• Prefer bounded fixes with clear owner and rollback boundary over broad tuning bundles.

Common pitfalls

• Optimizing synthetic kernels without production-shape validation.

• Reading average latency while ignoring p95 and p99 behavior.

• Declaring sparse or precision wins without fallback and quality evidence.

Principal accelerator review addendum

Systolic Mesh Basics should be framed as a full-system behavior, not an isolated kernel trick. Production outcomes are set by model shape mix, compiler choices, runtime queueing policy, memory hierarchy limits, and silicon delivery margins.

A systolic array spatially maps multiply-accumulate work onto a grid of processing elements (PEs) where activations and weights move rhythmically between neighbors. Instead of repeatedly fetching operands from global memory, data is reused as it flows across rows and columns, while partial sums propagate along deterministic paths. This regular communication pattern simplifies timing closure, routing, and control relative to highly dynamic fabrics, but requires careful launch scheduling so wavefronts arrive in lockstep. Practical performance therefore depends on matching tile dimensions, operand streaming cadence, and pipeline latency balancing across the mesh. A useful explanation always ties observed symptom to a repeatable path where useful work was blocked, delayed, or diluted by overhead.

Use Sustained MAC utilization versus theoretical peak under target GEMM shapes and memory-feed constraints. as an alarm, then anchor action using hard evidence such as Wavefront timing worksheet with PE occupancy trace and per-tile feed/drain schedule..

Systolic performance is primarily a data-delivery and mapping discipline problem. Senior reviews expect a chain of proof: workload intent -> mapping -> hardware behavior -> product impact.

Use this addendum to force explicit owner assignment, bounded fixes, and reproducible evidence before declaring closure.