Systolic Mesh Basics: Interview Drills

Interview drills

Interview Drills for Systolic Mesh Basics is anchored on Sustained MAC utilization versus theoretical peak under target GEMM shapes and memory-feed constraints.. Convert measurements into mechanism-backed decisions with clear owner accountability.

PROMPT
You observe regression in Sustained MAC utilization versus theoretical peak under target GEMM shapes and memory-feed constraints. for Systolic Mesh Basics. Explain root cause and release decision.

STRONG ANSWER
1. Defines workload and first failing mechanism.
2. Explains mechanism: A systolic array spatially maps multiply-accumulate work onto a grid of processing elements (PEs) where activations and weights move rhythmically between neighbors. Instead of repeatedly fetching operands from global memory, data is reused as it flows across rows and columns, while partial sums propagate along deterministic paths. This regular communication pattern simplifies timing closure, routing, and control relative to highly dynamic fabrics, but requires careful launch scheduling so wavefronts arrive in lockstep. Practical performance therefore depends on matching tile dimensions, operand streaming cadence, and pipeline latency balancing across the mesh.
3. Requests proving artifact: Wavefront timing worksheet with PE occupancy trace and per-tile feed/drain schedule.
4. Proposes bounded fix + owner + rollback-safe validation.

WEAK ANSWER
Gives generic optimization ideas without mechanism proof or ownership.

AI accelerator deep dive

Systolic efficiency is governed by feed quality, tile fit, and bubble control.

Concept diagram

SYSTOLIC WAVEFLOW

operand stream -> wavefront launch -> PE mesh compute -> reduction/writeback
                         ^ bubbles and feed stalls reduce realized throughput

Metric graph

UTILIZATION LOSSES

tile mismatch      ███████
feed stalls        █████████
sync bubbles       █████

Metrics and artifacts to collect

• mesh occupancy timeline

• fill-drain overhead

• tile mismatch histogram

• DRAM stall attribution

Mini case study

Increasing mesh size did not help until scheduling and tile alignment removed persistent wavefront bubbles.

Debug branches

• Measure bubble source first

• Classify compute vs memory starvation

• Tune tile policy before frequency changes

Senior review question

Ask: which first-principles bottleneck class explains the symptom, and what artifact proves it reproducibly?

Key takeaways

• Tie every accelerator claim to a reproducible workload slice and one primary metric trend.

• Prefer bounded fixes with clear owner and rollback boundary over broad tuning bundles.

Common pitfalls

• Optimizing synthetic kernels without production-shape validation.

• Reading average latency while ignoring p95 and p99 behavior.

• Declaring sparse or precision wins without fallback and quality evidence.

Interview answer expansion

A strong answer on Systolic Mesh Basics names the workload symptom, explains mechanism (A systolic array spatially maps multiply-accumulate work onto a grid of processing elements (PEs) where activations and weights move rhythmically between neighbors. Instead of repeatedly fetching operands from global memory, data is reused as it flows across rows and columns, while partial sums propagate along deterministic paths. This regular communication pattern simplifies timing closure, routing, and control relative to highly dynamic fabrics, but requires careful launch scheduling so wavefronts arrive in lockstep. Practical performance therefore depends on matching tile dimensions, operand streaming cadence, and pipeline latency balancing across the mesh.), and proposes one measurable validation plan.

Then it identifies owner and fallback action if the proposed fix under-delivers.

The goal is practical engineering reasoning, not keyword listing.