Weight-Stationary Dataflow: Debug Playbook

Debug playbook

Debug Playbook for Weight-Stationary Dataflow is anchored on Weight reuse factor and off-array weight bandwidth per tera-operations for representative inference layers.. Convert measurements into mechanism-backed decisions with clear owner accountability.

1. Freeze workload seed, model revision, and execution environment.

2. Locate first persistent stage where metrics diverge.

3. Classify dominant mechanism: compute, memory, scheduling, precision, or thermal.

4. Build one focused reproducer and apply one bounded fix.

5. Re-run full correctness, quality, and performance matrix.

Review memo template

ACCELERATOR REVIEW MEMO - Systolic Arrays / Weight-Stationary Dataflow

1. Symptom
   - Failing metric: Weight reuse factor and off-array weight bandwidth per tera-operations for representative inference layers.
   - Workload or traffic slice: <name>
   - First failing layer or stage: <operator, schedule, memory, runtime>
   - Build and runtime tags: <compiler/firmware/runtime/hardware>

2. Mechanism hypothesis
   - Primary mechanism: In weight-stationary scheduling, each PE holds a weight value (or small filter fragment) for multiple cycles while activations stream through the mesh. Keeping weights local reduces expensive weight fetch traffic and is especially attractive for convolutional and batched inference workloads where filters are reused heavily across many input windows. The tradeoff is that activation movement and partial-sum routing can become dominant bandwidth or latency bottlenecks if tiling is not aligned to on-chip buffer capacity. Effective designs co-optimize filter blocking, activation prefetch, and reload cadence so stationary weights remain fully productive instead of idling between tiles.
   - Competing hypotheses: <dataflow mismatch, memory stalls, precision drift, thermal limits>
   - Missing evidence: <counter packet, trace, replay, signoff data>

3. Proposed action
   - Smallest reversible change: <mapping/runtime/policy/config>
   - Expected movement: <throughput, p99 latency, perf-per-watt>
   - Regression risk: correctness, quality, thermal, software compatibility

4. Signoff
   - Required artifact: Dataflow mapping report showing weight residency, activation traffic, and buffer pressure by layer type.
   - Required owners: accelerator architect, compiler mapping owner, SRAM subsystem owner, runtime scheduler owner, model performance owner
   - Final decision: ship, bounded rollout, rollback, or escalate

AI accelerator deep dive

Systolic efficiency is governed by feed quality, tile fit, and bubble control.

Concept diagram

SYSTOLIC WAVEFLOW

operand stream -> wavefront launch -> PE mesh compute -> reduction/writeback
                         ^ bubbles and feed stalls reduce realized throughput

Metric graph

UTILIZATION LOSSES

tile mismatch      ███████
feed stalls        █████████
sync bubbles       █████

Metrics and artifacts to collect

• mesh occupancy timeline

• fill-drain overhead

• tile mismatch histogram

• DRAM stall attribution

Mini case study

Increasing mesh size did not help until scheduling and tile alignment removed persistent wavefront bubbles.

Debug branches

• Measure bubble source first

• Classify compute vs memory starvation

• Tune tile policy before frequency changes

Senior review question

Ask: which first-principles bottleneck class explains the symptom, and what artifact proves it reproducibly?

Key takeaways

• Tie every accelerator claim to a reproducible workload slice and one primary metric trend.

• Prefer bounded fixes with clear owner and rollback boundary over broad tuning bundles.

Common pitfalls

• Optimizing synthetic kernels without production-shape validation.

• Reading average latency while ignoring p95 and p99 behavior.

• Declaring sparse or precision wins without fallback and quality evidence.

Principal accelerator review addendum

Weight-Stationary Dataflow should be framed as a full-system behavior, not an isolated kernel trick. Production outcomes are set by model shape mix, compiler choices, runtime queueing policy, memory hierarchy limits, and silicon delivery margins.

In weight-stationary scheduling, each PE holds a weight value (or small filter fragment) for multiple cycles while activations stream through the mesh. Keeping weights local reduces expensive weight fetch traffic and is especially attractive for convolutional and batched inference workloads where filters are reused heavily across many input windows. The tradeoff is that activation movement and partial-sum routing can become dominant bandwidth or latency bottlenecks if tiling is not aligned to on-chip buffer capacity. Effective designs co-optimize filter blocking, activation prefetch, and reload cadence so stationary weights remain fully productive instead of idling between tiles. A useful explanation always ties observed symptom to a repeatable path where useful work was blocked, delayed, or diluted by overhead.

Use Weight reuse factor and off-array weight bandwidth per tera-operations for representative inference layers. as an alarm, then anchor action using hard evidence such as Dataflow mapping report showing weight residency, activation traffic, and buffer pressure by layer type..

Systolic performance is primarily a data-delivery and mapping discipline problem. Senior reviews expect a chain of proof: workload intent -> mapping -> hardware behavior -> product impact.

Use this addendum to force explicit owner assignment, bounded fixes, and reproducible evidence before declaring closure.