Verification & Silicon Bring-up

Section goal

From pre-silicon closure to lab debug, this section covers how accelerator teams validate correctness, performance, and reliability before and after tapeout.

How to study this section

1. Start with each topic hub and restate the mechanism in your own words.

2. Use reports and debug pages to separate symptoms from root causes.

3. Practice worked examples and interview drills under fixed metadata.

4. Close with checklist and silicon impact before making release claims.

Topics

1. accelerator-verification-strategy/ - Accelerator Verification Strategy

2. perf-counter-and-profiling/ - Performance Counters and Profiling for Bring-up

3. power-virus-thermal-test/ - Power Virus and Thermal Stress Testing

4. post-silicon-accelerator-debug/ - Post-Silicon Accelerator Debug

Related topics

• AI Accelerator course hub

AI accelerator deep dive

Bring-up speed and correctness depend on designed-in observability and replayable debug flow.

Concept diagram

BRING-UP EVIDENCE LOOP

failure symptom -> trace packet -> replay -> isolate root cause -> bounded fix

Metric graph

OBSERVABILITY VALUE

directed tests only      ██████████
plus counters            ███████
plus trace and replay    ███

Metrics and artifacts to collect

• counter completeness

• trace trigger coverage

• replay success rate

• escape-risk trend

Mini case study

A silicon-only regression closed quickly because trace identity and counter alignment were planned before tapeout.

Debug branches

• Start from first failing trace window

• Align software and hardware timestamps

• Demand reversible owner fix before signoff

Senior review question

Ask: which first-principles bottleneck class explains the symptom, and what artifact proves it reproducibly?