Analog for Digital Engineers · All levels

ADCs (Analog-to-Digital)

Core ADC theory and architecture choices for digital engineers: sampling/quantization fundamentals, SAR and pipeline tradeoffs, delta-sigma noise-shaping, and practical interpretation of ENOB/SNDR/SFDR/INL/DNL.

Section goal

How to study this section

Start with each topic hub and restate the mechanism in your own words.
Use reports and debug pages to classify first failing boundaries.
Practice worked examples and interview drills under fixed setup metadata.
Close with checklist and execution impact before signoff claims.

Topics

adc-fundamentals/ - Sampling, Quantization, and Nyquist Reality
sar-and-pipeline-adc/ - SAR vs Pipeline ADC Architectures
delta-sigma-adc/ - Delta-Sigma ADC: Oversampling and Noise Shaping
adc-metrics-enob-sndr/ - Interpreting ENOB, SNDR, SFDR, INL, and DNL

Analog deep dive

ADC success comes from aligning sampling assumptions, architecture constraints, and metric interpretation.

Concept diagram

diagram

ADC VALIDATION FLOW

front-end assumptions -> sampler behavior -> quantization path -> metric interpretation

Metric graph

diagram

ADC FAILURE MIX

aliasing leakage         ████
jitter-limited SNR       █████
metric misuse            ███

Metrics and artifacts to collect

alias and blocker folding map
clock-jitter impact estimate
architecture throughput/latency fit
ENOB/SNDR/SFDR context table

Mini case study

ENOB shortfall resolved after anti-alias assumptions and clock quality were corrected, without changing core quantizer logic.

Debug branches

Verify coherent sampling and FFT setup before root-cause claims.
Classify whether loss is noise, distortion, or folded interference.
Audit architecture-fit assumptions against workload bandwidth.

Senior review question

Ask: which source-path-victim boundary failed first, and which artifact proves it reproducibly?

Practice this lesson

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