DAC Architectures: R-2R, Current-Steering, and Charge-Redistribution

What this topic teaches

DAC Architectures: R-2R, Current-Steering, and Charge-Redistribution turns analog principles into staff-level mixed-signal execution decisions. R-2R ladder DACs use repeated resistor ratios to realize binary weighting with relatively compact matching requirements, making them attractive for moderate speed and moderate resolution but sensitive to resistor gradient and switch resistance variation. Current-steering DACs route matched current sources to output nodes and scale best to high sample rates; however, dynamic mismatch, switch timing skew, and output compliance effects can dominate SFDR if segmentation and clocking are not carefully engineered. Charge-redistribution DACs (capacitive DACs) move and share charge among binary-weighted or segmented capacitors, enabling excellent static linearity in many CMOS processes and natural integration with SAR-style switching networks, but capacitor parasitics, reference settling, and top-plate switching transients constrain speed. Real products often use segmented hybrids (thermometer + binary tails) to reduce major-carry glitches while controlling area and decoder complexity. Architecture choice is therefore workload-driven: required bandwidth, spur mask, power budget, and calibration strategy matter more than headline resolution alone.

Senior-engineer framing question

When Area-power-linearity tradeoff versus update rate, including glitch energy and settling time across architecture options. regresses, can you isolate the first failing boundary, prove the mechanism, assign owner, and close with rollback-safe validation?

ANALOG EXECUTION FLOW - DAC Architectures: R-2R, Current-Steering, and Charge-Redistribution

assumptions and operating profile
      |
      v
source-path-victim mapping
      |
      v
measurement/model evidence
      |
      v
bounded mitigation and replay
      |
      v
release decision with rollback guard

Evidence to collect

• Primary metric: Area-power-linearity tradeoff versus update rate, including glitch energy and settling time across architecture options..

• Primary artifact: Architecture selection matrix comparing R-2R, current-steering, and capacitive DAC paths by speed, SFDR, power, and implementation risk..

• Owners to include: mixed-signal architect, circuit designer, layout matching owner, clocking and timing owner, system performance owner.

• One reproducible failing workload and one controlled comparator run.

• One fixed metadata run with board, mode, and environmental tags locked.

Ownership layers

OWNERSHIP LAYERS - DAC Architectures: R-2R, Current-Steering, and Charge-Redistribution

+----------------------+--------------------------------+--------------------------------+
| Team                 | Primary responsibility         | Closure artifact               |
+----------------------+--------------------------------+--------------------------------+
| mixed-signal architect | mechanism and margin ownership  | design rationale + constraints |
| circuit designer | integration and runtime behavior | contract + telemetry evidence  |
| layout matching owner | bench closure and rollout gates | stress matrix + signoff memo   |
+----------------------+--------------------------------+--------------------------------+

Decision matrix

EVIDENCE MATRIX - DAC Architectures: R-2R, Current-Steering, and Charge-Redistribution

+-----------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence                    | Tells you                      | Does not prove                 | Next action               |
+-----------------------------+--------------------------------+--------------------------------+---------------------------+
| setup calibration logs      | measurement chain validity     | mechanism root cause           | pair with transfer checks |
| spectrum and jitter plots   | frequency-domain behavior      | ownership of failure           | correlate with activity   |
| PVT corner overlays         | sensitivity distribution       | runtime workload equivalence   | add workload replay       |
| model-vs-silicon deltas     | assumption mismatch classes    | direct fix correctness         | test bounded mitigation   |
| before-after matrix         | mitigation movement            | long-term field drift          | run stress suites         |
+-----------------------------+--------------------------------+--------------------------------+---------------------------+

Key takeaways

• Classify mechanism and boundary before proposing architecture-wide fixes.

• Tie each claim to one proving artifact and one accountable owner.

• Close with stress replay and explicit rollback criteria.

Common pitfalls

• Treating nominal-corner success as sufficient closure evidence.

• Changing multiple analog knobs and losing causality.

• Skipping setup-fidelity audits before attributing failures to silicon.

Analog deep dive

DAC closure needs both static transfer quality and dynamic glitch/spectral discipline.

Concept diagram

DAC OUTPUT CHAIN

code mapping -> switching network -> output path -> reconstruction filter

Metric graph

DAC RISK MIX

major-carry glitches     █████
settling residuals       ████
image leakage            ███

Metrics and artifacts to collect

• INL/DNL sweep package

• glitch energy and settling trend

• SFDR/THD versus output frequency

• reconstruction filter compliance

Mini case study

Good static linearity masked dynamic spur failures driven by switching asymmetry and insufficient reconstruction margin.

Debug branches

• Tie static transfer plots to dynamic spectral outcomes.

• Inspect major-carry behavior separately from small-step transitions.

• Validate output path with realistic load and package parasitics.

Senior review question

Ask: which source-path-victim boundary failed first, and which artifact proves it reproducibly?

Key takeaways

• Tie every analog claim to one measurable metric and one proving artifact.

• Prefer minimal reversible mitigations with explicit owner and rollback criteria.

Common pitfalls

• Treating all noise as one scalar instead of path and frequency dependent behavior.

• Changing multiple analog knobs at once and losing causality.

• Declaring closure from nominal behavior without stress replay evidence.