Analog for Digital Engineers · All levels
DACs (Digital-to-Analog): Tricky Q&A
Senior interview and review questions for DACs (Digital-to-Analog).
Section Q&A bank
Use these drills after completing all topics in DACs (Digital-to-Analog). Answer with context, mechanism proof, artifact, owner, and release decision.
Why can a DAC show excellent INL/DNL on a slow ramp but poor SFDR on a sine output?
diagram
[INT][ANALOG][DATA-CONVERTERS-DAC]
Q: Why can a DAC show excellent INL/DNL on a slow ramp but poor SFDR on a sine output?
A:
INL/DNL are static or quasi-static transfer metrics, so they do not directly capture switching-time effects. SFDR is strongly affected by dynamic nonidealities such as code-dependent glitch energy, clock/feedthrough asymmetry, incomplete settling, and output path distortion. A DAC can be statically linear yet still generate strong spurs when transitions occur at high rate and nonuniform timing.
FOLLOW-UP TRAP: Assuming good INL/DNL guarantees good SFDR at operating bandwidth.Why are major-carry transitions often the worst-case glitch events in binary-weighted DACs?
diagram
[INT][ANALOG][DATA-CONVERTERS-DAC]
Q: Why are major-carry transitions often the worst-case glitch events in binary-weighted DACs?
A:
At major carries, many bits toggle simultaneously (for example 011111... to 100000...), so switch timing mismatch briefly drives an incorrect intermediate sum. That transient charge/current error appears as glitch impulse energy, which then maps into wideband spectral artifacts and tone spurs. Segmentation and carefully aligned switching reduce this effect by minimizing large simultaneous binary-weight jumps.
FOLLOW-UP TRAP: Treating glitch as random noise unrelated to code transition structure.What does the zero-order-hold model imply about reconstruction filtering even when baseband looks correct in time domain?
diagram
[INT][ANALOG][DATA-CONVERTERS-DAC]
Q: What does the zero-order-hold model imply about reconstruction filtering even when baseband looks correct in time domain?
A:
ZOH means the DAC output inherently contains spectral images around sampling-frequency multiples with a sinc amplitude envelope. A waveform can look acceptable on a low-bandwidth scope yet still violate spectral masks because image energy remains high. Reconstruction filters are required to suppress these images, not just to smooth visible staircase edges.
FOLLOW-UP TRAP: Believing interpolation in digital logic alone eliminates the need for analog reconstruction filtering.When choosing between R-2R, current-steering, and capacitive DACs, what is the common architectural mistake?
diagram
[INT][ANALOG][DATA-CONVERTERS-DAC]
Q: When choosing between R-2R, current-steering, and capacitive DACs, what is the common architectural mistake?
A:
The common mistake is selecting by nominal resolution only. Real suitability depends on sample rate, spur requirements, reference drive complexity, calibration plan, and process-dependent matching behavior. Architecture decisions that ignore dynamic specs and implementation context usually fail late, when measured SFDR, settling, or power diverges from spreadsheet expectations.
FOLLOW-UP TRAP: Picking architecture from bit-depth and area alone without dynamic and calibration constraints.Q&A drill guide
diagram
SYMPTOM -> ANALOG MECHANISM -> EVIDENCE -> OWNER ACTION -> VALIDATIONSketch while answering
diagram
DAC OUTPUT CHAIN
code mapping -> switching network -> output path -> reconstruction filterCommon traps
Tie static transfer plots to dynamic spectral outcomes.
Inspect major-carry behavior separately from small-step transitions.
Validate output path with realistic load and package parasitics.
Key takeaways
Tie every analog claim to one measurable metric and one proving artifact.
Prefer minimal reversible mitigations with explicit owner and rollback criteria.
Common pitfalls
Treating all noise as one scalar instead of path and frequency dependent behavior.
Changing multiple analog knobs at once and losing causality.
Declaring closure from nominal behavior without stress replay evidence.