Analog for Digital Engineers · All levels

Scenario: ADC ENOB Shortfall - Interview Scenario

Bench FFT shows ENOB below target although static ramp tests and digital capture logic appear healthy. Failures grow with input frequency and board activity.

Scenario

Bench FFT shows ENOB below target although static ramp tests and digital capture logic appear healthy. Failures grow with input frequency and board activity.

diagram
OBSERVED METRIC
Measured ENOB/SNDR remains below signoff expectation across corner frequencies and stress conditions.

45-MINUTE INTERVIEW FLOW
0-5: define context and KPI
5-15: classify first failing boundary
15-25: identify proving artifact packet
25-35: propose bounded fix with owner
35-45: define validation matrix and rollback

Common traps to avoid

  • Assuming good INL/DNL guarantees dynamic ENOB/SNDR closure.

  • Blaming quantizer design before validating clock-quality and anti-alias assumptions.

  • Skipping setup-floor and coherent-sampling checks in the FFT methodology.

Scenario debrief

Score response quality on mechanism classification, proving artifact, owner assignment, and rollback-safe mitigation.

diagram
assumption -> mechanism -> evidence -> mitigation -> replay
diagram
risk reduction trend

Debrief prompts

  1. Which boundary failed first and how is it proven?

  2. Which analog mechanism best explains the symptom?

  3. What bounded fix closes risk with the smallest collateral change?

Key takeaways

  • Tie every analog claim to one measurable metric and one proving artifact.

  • Prefer minimal reversible mitigations with explicit owner and rollback criteria.

Common pitfalls

  • Treating all noise as one scalar instead of path and frequency dependent behavior.

  • Changing multiple analog knobs at once and losing causality.

  • Declaring closure from nominal behavior without stress replay evidence.