Noise & Signal Integrity: Tricky Q&A

[INT][ANALOG][NOISE-AND-SIGNAL-INTEGRITY]

Q: Why can enlarging MOS input devices lower 1/f noise but still fail to improve total integrated noise?

A:
Larger devices reduce flicker noise density by averaging more traps, but they also increase gate capacitance that can force higher source impedance interaction, slower settling, and potentially more sampled kT/C or bandwidth-limited noise integration elsewhere in the chain. If the signal band and sampling dynamics are not re-optimized, white-noise and settling penalties can offset 1/f gains. Total noise improvement requires system-level rebudgeting, not only transistor area scaling.

FOLLOW-UP TRAP: Assuming lower flicker density in one device automatically lowers whole-path RMS noise.

[INT][ANALOG][NOISE-AND-SIGNAL-INTEGRITY]

Q: A block shows 70 dB PSRR at 1 kHz. Why is that insufficient to guarantee immunity from switching-regulator ripple?

A:
Regulator ripple and digital aggressors often sit at much higher frequencies where loop gain has rolled off and PSRR may degrade dramatically, allowing direct feedthrough to output or references. Harmonic content can also intermodulate with clocks and appear as deterministic spurs even when low-frequency rejection looks excellent. You need PSRR across the relevant spectrum plus realistic supply impedance and activity profiles, not a single low-frequency number.

FOLLOW-UP TRAP: Treating one PSRR data-sheet point as broadband rejection.

[INT][ANALOG][NOISE-AND-SIGNAL-INTEGRITY]

Q: If your signal of interest is below Nyquist, why can aliases still dominate converter output?

A:
Because blockers and broadband noise above Nyquist fold into baseband after sampling unless sufficiently attenuated by the analog front-end filter. Once folded, aliases are mathematically inseparable from wanted in-band components in digital processing. Practical anti-alias design must consider out-of-band environment, not only desired-band placement.

FOLLOW-UP TRAP: Believing Nyquist compliance of the wanted tone alone prevents alias corruption.

[INT][ANALOG][NOISE-AND-SIGNAL-INTEGRITY]

Q: How do jitter and phase noise describe the same clock quality, and why does integration range matter?

A:
Phase noise is the spectral density of phase fluctuations; integrating it over a specified offset-frequency band yields RMS phase error, which converts to RMS timing jitter. Different integration bounds can produce very different jitter values, so quoted numbers are meaningless without offset limits and transfer-function context. Endpoint impact depends on how PLL and path filtering weight close-in versus far-out noise.

FOLLOW-UP TRAP: Comparing jitter specs directly when vendors used different phase-noise integration bands.

SYMPTOM -> ANALOG MECHANISM -> EVIDENCE -> OWNER ACTION -> VALIDATION

NOISE PATH VIEW

source -> transfer function -> victim sensitivity -> system margin