Analog for Digital Engineers · All levels

Supply Noise Coupling Paths and PSRR Across Frequency: Debug Playbook

Debug Playbook for Supply Noise Coupling Paths and PSRR Across Frequency.

Debug playbook

Debug Playbook for Supply Noise Coupling Paths and PSRR Across Frequency is anchored on PSRR(dB) versus frequency, output spur amplitude at switching harmonics, and supply-induced ENOB/SNDR degradation.. Convert observations into mechanism-backed and owner-bound actions.

Freeze setup, workload, and corner metadata.
Locate first persistent mechanism divergence.
Classify mechanism family: loop, coupling, sampling, noise, or interface.
Apply one focused reproducer and one bounded fix.
Re-run representative stress and replay matrix.

Review memo template

diagram

ANALOG REVIEW MEMO - Noise & Signal Integrity / Supply Noise Coupling Paths and PSRR Across Frequency

1. Symptom
   - Failing metric: PSRR(dB) versus frequency, output spur amplitude at switching harmonics, and supply-induced ENOB/SNDR degradation.
   - Trigger context: <workload/mode/corner>
   - First failing boundary: <source/path/victim>

2. Mechanism hypothesis
   - Candidate mechanism: Power-supply noise reaches sensitive nodes through finite gain-stage rejection, bias mirrors, substrate coupling, package parasitics, and shared return inductance that converts di/dt into local ground bounce. PSRR is strongly frequency-dependent: low-frequency rejection can be high due to loop gain, then collapse near amplifier poles where feedthrough and parasitic capacitances dominate. Digital switching regulators and clock trees inject deterministic ripple and harmonics that can mix with signal paths, creating spurs in converters and sidebands in PLL or SerDes clocks. Robust design combines local decoupling impedance shaping, low-noise references/LDO partitioning, star-domain isolation strategy, and layout discipline (current return control, guard structures, deep-nwell where available), while system teams validate worst-case coupling using realistic package/board impedance and simultaneous-switching activity.
   - Competing hypotheses: noise, coupling, loop, sampling, interface
   - Missing evidence: <measurement/model/trace>

3. Proposed action
   - Smallest reversible change: <design/layout/config/firmware>
   - Expected movement: <metric trend>
   - Regression risk: compatibility, stability, maintainability

4. Signoff
   - Required artifact: End-to-end supply-coupling map from board rail to critical analog nodes with PSRR-vs-frequency limits and spur budget signoff.
   - Required owners: power integrity owner, analog macro designer, package and board engineer, SoC integration owner, post-silicon validation owner
   - Final decision: ship, bounded rollout, rollback, or escalate

Analog deep dive

Noise and SI closure is achieved by frequency-aware path analysis, not one-number guard-bands.

Concept diagram

diagram

NOISE PATH VIEW

source -> transfer function -> victim sensitivity -> system margin

Metric graph

diagram

NOISE CLOSURE

path unknown             ██████
path classified          █████████
validated mitigations    ███████

Metrics and artifacts to collect

white/1-f noise decomposition
PSRR versus frequency profile
alias-folding sensitivity map
phase-noise to jitter integration summary

Mini case study

A broadband spur issue persisted until teams modeled package and return-path coupling instead of relying on low-frequency PSRR numbers.

Debug branches

Classify deterministic versus random contributors first.
Map dominant transfer path before adding generic filtering.
Use operating-mode-specific aggressor profiles in validation.

Senior review question

Ask: which source-path-victim boundary failed first, and which artifact proves it reproducibly?

Key takeaways

Tie every analog claim to one measurable metric and one proving artifact.
Prefer minimal reversible mitigations with explicit owner and rollback criteria.

Common pitfalls

Treating all noise as one scalar instead of path and frequency dependent behavior.
Changing multiple analog knobs at once and losing causality.
Declaring closure from nominal behavior without stress replay evidence.

Debug ladder

Sequence: classify -> isolate path -> prove mechanism -> bounded mitigation -> replay.

Avoid multi-axis fixes before first boundary is proven.

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