PLLs & Clock Generation

Section goal

Phase-locked and delay-locked clock systems from circuit blocks to SoC integration, with practical tradeoffs among lock time, jitter, spur behavior, power, and distribution strategy.

How to study this section

1. Start with each topic hub and restate the mechanism in your own words.

2. Use reports and debug pages to classify first failing boundaries.

3. Practice worked examples and interview drills under fixed setup metadata.

4. Close with checklist and execution impact before signoff claims.

Topics

1. pll-architecture/ - PLL Architecture: PFD, Charge Pump, Loop Filter, VCO, and Divider

2. vco-and-charge-pump/ - VCO and Charge Pump Design Limits

3. loop-dynamics-and-jitter/ - Loop Bandwidth, Damping, and Jitter Tradeoffs

4. dll-and-clock-generation/ - DLL vs PLL and On-Chip Clock Generation Strategy

Related topics

• Analog for Digital course hub

Analog deep dive

Clock-loop closure balances lock behavior, spur hygiene, and endpoint jitter in one control framework.

Concept diagram

CLOCK QUALITY LOOP

loop design -> transfer shaping -> integration stress -> timing margin

Metric graph

CLOCKING FAILURES

spur excursions          ████
jitter peaking           █████
transition instability   ███

Metrics and artifacts to collect

• loop bandwidth and damping table

• noise-transfer decomposition

• reference spur budget

• mode-transition jitter trend

Mini case study

Fast lock tuning improved startup but amplified deterministic jitter under supply stress during DVFS transitions.

Debug branches

• Confirm which jitter band maps to the failing endpoint.

• Separate CP/loop artifacts from reference-source limitations.

• Validate with transition-aware workloads, not only steady-state lock tests.

Senior review question

Ask: which source-path-victim boundary failed first, and which artifact proves it reproducibly?