CPU Design · All levels

Predictor Types and Accuracy

Branch Prediction & Speculation: Local, global, hybrid, and neural-style predictors trade storage, latency, and aliasing behavior; tuning confidence and update policy determines real-world stability under changing branch patterns.

What this topic teaches

Predictor Types and Accuracy turns CPU design theory into actionable review decisions. Local, global, hybrid, and neural-style predictors trade storage, latency, and aliasing behavior; tuning confidence and update policy determines real-world stability under changing branch patterns. The target is evidence-backed closure, not opinion-driven tuning.

Senior-engineer framing question

When global prediction accuracy, MPKI, and confidence calibration error shifts, can you prove first failing stage, dominant mechanism, accountable owner, and release-safe mitigation?

diagram

CPU PIPELINE VIEW - Predictor Types and Accuracy

fetch -> decode -> rename -> dispatch -> execute -> retire
  |        |         |          |         |         |
icache   uop flow   map table  queueing  FU ports  ROB commit

steady-state goal:
keep every stage supplied without bubbles or flush storms

Focus: connect metric movement to the first stage loss
Metric tracked: global prediction accuracy, MPKI, and confidence calibration error

Architecture visuals

Draw the mechanism before changing knobs. These visuals are optimized for design reviews and interview whiteboards.

Predictor family behavior

diagram

BRANCH PREDICTOR VIEW - Predictor Types and Accuracy

fetch PC -> BTB lookup -> direction predictor -> target select -> fetch redirect
               |               |                    |
          BTB miss cost     confidence         RAS / indirect path

branch resolves in execute:
correct prediction  -> pipeline keeps flowing
mispredict          -> flush + restart + refill

Focus: compare local/global/hybrid confidence and aliasing behavior

Accuracy tuning improvement curve

diagram

BEFORE / AFTER TREND - Predictor Types and Accuracy

metric quality
  ^
  |                        o target region
  |                 o post-fix rerun
  |            o
  |      o baseline (failing)
  +----------------------------------------------> iteration
      capture       isolate mechanism       close

Use this to prove improvement is causal and stable.

Out-of-order control map

diagram

OOO CORE BLOCK DIAGRAM - Predictor Types and Accuracy

decode -> rename -> dispatch -> reservation stations -> execute units
             |                        |                    |
       free-list / map table       wakeup-select         writeback
             \                        |                    /
              +-------- reorder buffer / retire ---------+

Focus: rename to retire dataflow

Memory hierarchy map

diagram

CPU CACHE + MEMORY HIERARCHY - Predictor Types and Accuracy

                 [ L1I ]   [ L1D ]
               32-64KB, ~4 cycles
                      \     /
                       [  L2  ]
                 512KB-2MB, ~12 cycles
                           |
                         [ L3 ]
               shared LLC, 30-60 cycles
                           |
                    [ DDR/HBM memory ]
                    80-150ns effective

Optimization lens: latency vs capacity tradeoff

Speculation lens

diagram

BRANCH PREDICTOR VIEW - Predictor Types and Accuracy

fetch PC -> BTB lookup -> direction predictor -> target select -> fetch redirect
               |               |                    |
          BTB miss cost     confidence         RAS / indirect path

branch resolves in execute:
correct prediction  -> pipeline keeps flowing
mispredict          -> flush + restart + refill

Focus: minimize wrong-path work

Ownership layers

diagram

CPU OWNERSHIP LAYERS - Predictor Types and Accuracy

artifact area     owner
----------------  ----------------------------
architecture    branch predictor architect
RTL/microarch   predictor RTL owner
software/tools  perf modeling lead

Rule: every regressed metric must map to an explicit owner and closure artifact.

Evidence required

Primary metric: global prediction accuracy, MPKI, and confidence calibration error.
Primary artifact: predictor-type comparison matrix, accuracy-by-workload plot, and confidence histogram.
Owners to include: branch predictor architect, predictor RTL owner, perf modeling lead.
One reproducible failing workload and one stable comparator run.
One run with fully locked environment metadata for causal comparison.

Compute-memory limit lens

diagram

CPU ROOFLINE - Predictor Types and Accuracy

performance
   ^
   |                 compute roof
   |                /
   |               /
   |--------------/---------------- memory roof
   +----------------------------------------------> arithmetic intensity
      memory-bound                 compute-bound

Interpretation: separate compute and memory limits

Key takeaways

Classify stage loss before proposing fixes.
Use artifacts to separate mechanism from symptoms.
Close with owner accountability and rollback criteria.

Common pitfalls

Using average IPC alone while ignoring tail behavior.
Comparing traces across mismatched binaries or thermal states.
Calling closure without workload-level validation.

CPU deep dive

Speculation helps only when wrong-path cost and recovery bandwidth are tightly controlled.

Concept diagram

diagram

SPECULATION LOOP

predict direction/target -> speculative fetch/decode -> resolve -> flush/recover

Metric graph

diagram

SPECULATION COST MIX

wrong-path decode work  █████
flush recovery delay    ████
refill starvation       ███

Reports and artifacts

branch accuracy by workload
BTB/RAS pressure report
mispredict recovery timeline
bad-speculation CPI share

Mini case study

Indirect branch aliasing in one service raised wrong-path work enough to dominate total CPI despite high ALU utilization.

Debug branches

Break down mispredicts by branch family and code region
Measure flush depth and refill bandwidth separately
Validate predictor changes under security mitigation settings

Senior review question

Ask: which CPI/latency evidence proves this topic is truly closed beyond synthetic benchmarks?

Key takeaways

Always connect microarchitectural counter changes to product workload outcomes.
Lock binary, compiler, firmware, and thermal metadata before comparing CPU traces.

Common pitfalls

Treating average IPC as sufficient proof while ignoring latency tails and outliers.
Applying predictor or prefetch tweaks without first-failing-stage attribution.
Declaring closure without reproducible perf, correctness, and power gates.

Practice this lesson