CPU Design · All levels
L2/L3 Hierarchy Design: Interview Drills
Interview Drills for L2/L3 Hierarchy Design.
Interview drills
Interview Drills for L2/L3 Hierarchy Design centers on LLC hit rate, inter-core interference index, and effective memory latency. Tie every claim to a measurable artifact and an owner-controlled action.
PROMPT
You observe LLC hit rate, inter-core interference index, and effective memory latency on L2/L3 Hierarchy Design. Walk through root cause and release decision.
STRONG ANSWER
1. Names failing workload and first stage loss.
2. Explains mechanism: Private and shared cache layers must balance locality, coherence traffic, and QoS isolation so one core's bursty stream does not collapse latency for neighboring cores.
3. Requests proving artifact: LLC residency report, QoS contention matrix, and latency stack chart
4. Proposes bounded fix + owner + rollback-safe validation.
WEAK ANSWER
Suggests generic optimization ideas without mechanism proof or owner accountability.Decision matrix
CPU EVIDENCE MATRIX - L2/L3 Hierarchy Design
+---------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence | Tells you | Does not prove | Next action |
+---------------------------+--------------------------------+--------------------------------+---------------------------+
| CPI + top-down stack | broad pressure domain | exact root mechanism | inspect first failing stage |
| PMU event timeline | temporal onset and persistence | causality by itself | pair with trace and config lock |
| pipeline occupancy trace | bubble origin and spread | multicore/system interactions | correlate with LLC/NoC data |
| cache/TLB/coherence logs | memory and translation health | scheduler fairness | inspect issue/port behavior |
| thermal + power telemetry | silicon operating envelope | architectural correctness | validate bounded fixes at same corners |
+---------------------------+--------------------------------+--------------------------------+---------------------------+CPU deep dive
Memory hierarchy closure needs cache, TLB, and prefetch policy to be tuned together for real latency tails.
Concept diagram
MEMORY + TRANSLATION STACK
L1I/L1D -> L2 -> LLC -> DRAM
| | |
ITLB/DTLB hierarchy + page walkersMetric graph
LATENCY TAIL CONTRIBUTORS
cache miss chains █████
translation misses ████
coherence interference ███Reports and artifacts
L1/L2/LLC latency stack
TLB walk profile
prefetch usefulness report
memory tail percentile dashboard
Mini case study
Prefetch aggressiveness improved average misses but worsened p99 latency by polluting LLC and stressing page walkers.
Debug branches
Tag misses by source: capacity, conflict, translation, or coherence
Track TLB shootdowns and page-size behavior with workload phases
Evaluate prefetch policy on tail latency, not just average CPI
Senior review question
Ask: which CPI/latency evidence proves this topic is truly closed beyond synthetic benchmarks?
Key takeaways
Always connect microarchitectural counter changes to product workload outcomes.
Lock binary, compiler, firmware, and thermal metadata before comparing CPU traces.
Common pitfalls
Treating average IPC as sufficient proof while ignoring latency tails and outliers.
Applying predictor or prefetch tweaks without first-failing-stage attribution.
Declaring closure without reproducible perf, correctness, and power gates.
Interview answer expansion
Strong interview answers for L2/L3 Hierarchy Design begin with workload and metric framing, then explain mechanism in plain terms: Private and shared cache layers must balance locality, coherence traffic, and QoS isolation so one core's bursty stream does not collapse latency for neighboring cores.
Then propose a measurement plan: CPI stack, branch quality, queue occupancy, cache/TLB behavior, and latency distribution as applicable.
Finally, present one bounded fix plus regression risk. CPU interviews reward explicit tradeoff ownership, not generic tuning advice.