CPU Design · All levels

Prefetch and Stream Buffers

Cache & Memory Hierarchy: Stride and stream predictors pull data ahead of demand; poorly tuned aggressiveness pollutes caches and consumes memory bandwidth that could serve useful misses.

What this topic teaches

Prefetch and Stream Buffers turns CPU design theory into actionable review decisions. Stride and stream predictors pull data ahead of demand; poorly tuned aggressiveness pollutes caches and consumes memory bandwidth that could serve useful misses. The target is evidence-backed closure, not opinion-driven tuning.

Senior-engineer framing question

When prefetch accuracy, coverage, and bandwidth waste ratio shifts, can you prove first failing stage, dominant mechanism, accountable owner, and release-safe mitigation?

diagram

CPU PIPELINE VIEW - Prefetch and Stream Buffers

fetch -> decode -> rename -> dispatch -> execute -> retire
  |        |         |          |         |         |
icache   uop flow   map table  queueing  FU ports  ROB commit

steady-state goal:
keep every stage supplied without bubbles or flush storms

Focus: connect metric movement to the first stage loss
Metric tracked: prefetch accuracy, coverage, and bandwidth waste ratio

Architecture visuals

Draw the mechanism before changing knobs. These visuals are optimized for design reviews and interview whiteboards.

Prefetch placement in hierarchy

diagram

CPU CACHE + MEMORY HIERARCHY - Prefetch and Stream Buffers

                 [ L1I ]   [ L1D ]
               32-64KB, ~4 cycles
                      \     /
                       [  L2  ]
                 512KB-2MB, ~12 cycles
                           |
                         [ L3 ]
               shared LLC, 30-60 cycles
                           |
                    [ DDR/HBM memory ]
                    80-150ns effective

Optimization lens: place stream buffers ahead of demand misses and eviction risk

Prefetch tuning before/after trend

diagram

BEFORE / AFTER TREND - Prefetch and Stream Buffers

metric quality
  ^
  |                        o target region
  |                 o post-fix rerun
  |            o
  |      o baseline (failing)
  +----------------------------------------------> iteration
      capture       isolate mechanism       close

Use this to prove improvement is causal and stable.

Out-of-order control map

diagram

OOO CORE BLOCK DIAGRAM - Prefetch and Stream Buffers

decode -> rename -> dispatch -> reservation stations -> execute units
             |                        |                    |
       free-list / map table       wakeup-select         writeback
             \                        |                    /
              +-------- reorder buffer / retire ---------+

Focus: rename to retire dataflow

Memory hierarchy map

diagram

CPU CACHE + MEMORY HIERARCHY - Prefetch and Stream Buffers

                 [ L1I ]   [ L1D ]
               32-64KB, ~4 cycles
                      \     /
                       [  L2  ]
                 512KB-2MB, ~12 cycles
                           |
                         [ L3 ]
               shared LLC, 30-60 cycles
                           |
                    [ DDR/HBM memory ]
                    80-150ns effective

Optimization lens: latency vs capacity tradeoff

Speculation lens

diagram

BRANCH PREDICTOR VIEW - Prefetch and Stream Buffers

fetch PC -> BTB lookup -> direction predictor -> target select -> fetch redirect
               |               |                    |
          BTB miss cost     confidence         RAS / indirect path

branch resolves in execute:
correct prediction  -> pipeline keeps flowing
mispredict          -> flush + restart + refill

Focus: minimize wrong-path work

Ownership layers

diagram

CPU OWNERSHIP LAYERS - Prefetch and Stream Buffers

artifact area     owner
----------------  ----------------------------
architecture    prefetch algorithm owner
RTL/microarch   memory controller owner
software/tools  performance analyst

Rule: every regressed metric must map to an explicit owner and closure artifact.

Evidence required

Primary metric: prefetch accuracy, coverage, and bandwidth waste ratio.
Primary artifact: prefetch usefulness report, stream-buffer occupancy trace, and bandwidth overhead chart.
Owners to include: prefetch algorithm owner, memory controller owner, performance analyst.
One reproducible failing workload and one stable comparator run.
One run with fully locked environment metadata for causal comparison.

Compute-memory limit lens

diagram

CPU ROOFLINE - Prefetch and Stream Buffers

performance
   ^
   |                 compute roof
   |                /
   |               /
   |--------------/---------------- memory roof
   +----------------------------------------------> arithmetic intensity
      memory-bound                 compute-bound

Interpretation: separate compute and memory limits

Key takeaways

Classify stage loss before proposing fixes.
Use artifacts to separate mechanism from symptoms.
Close with owner accountability and rollback criteria.

Common pitfalls

Using average IPC alone while ignoring tail behavior.
Comparing traces across mismatched binaries or thermal states.
Calling closure without workload-level validation.

CPU deep dive

Memory hierarchy closure needs cache, TLB, and prefetch policy to be tuned together for real latency tails.

Concept diagram

diagram

MEMORY + TRANSLATION STACK

L1I/L1D -> L2 -> LLC -> DRAM
   |       |      |
 ITLB/DTLB hierarchy + page walkers

Metric graph

diagram

LATENCY TAIL CONTRIBUTORS

cache miss chains      █████
translation misses     ████
coherence interference ███

Reports and artifacts

L1/L2/LLC latency stack
TLB walk profile
prefetch usefulness report
memory tail percentile dashboard

Mini case study

Prefetch aggressiveness improved average misses but worsened p99 latency by polluting LLC and stressing page walkers.

Debug branches

Tag misses by source: capacity, conflict, translation, or coherence
Track TLB shootdowns and page-size behavior with workload phases
Evaluate prefetch policy on tail latency, not just average CPI

Senior review question

Ask: which CPI/latency evidence proves this topic is truly closed beyond synthetic benchmarks?

Key takeaways

Always connect microarchitectural counter changes to product workload outcomes.
Lock binary, compiler, firmware, and thermal metadata before comparing CPU traces.

Common pitfalls

Treating average IPC as sufficient proof while ignoring latency tails and outliers.
Applying predictor or prefetch tweaks without first-failing-stage attribution.
Declaring closure without reproducible perf, correctness, and power gates.

Practice this lesson