CPU Design · All levels

Clock/Power Domains (CPU)

Physical Design, Perf & Bring-up: Clock and power partitioning enables frequency and energy scaling, but every domain crossing adds synchronization, reset sequencing, and intent verification burden.

What this topic teaches

Clock/Power Domains (CPU) turns CPU design theory into actionable review decisions. Clock and power partitioning enables frequency and energy scaling, but every domain crossing adds synchronization, reset sequencing, and intent verification burden. The target is evidence-backed closure, not opinion-driven tuning.

Senior-engineer framing question

When clock skew budget usage, CDC/RDC violation count, and power-state transition stability shifts, can you prove first failing stage, dominant mechanism, accountable owner, and release-safe mitigation?

diagram

CPU PIPELINE VIEW - Clock/Power Domains (CPU)

fetch -> decode -> rename -> dispatch -> execute -> retire
  |        |         |          |         |         |
icache   uop flow   map table  queueing  FU ports  ROB commit

steady-state goal:
keep every stage supplied without bubbles or flush storms

Focus: connect metric movement to the first stage loss
Metric tracked: clock skew budget usage, CDC/RDC violation count, and power-state transition stability

Architecture visuals

Draw the mechanism before changing knobs. These visuals are optimized for design reviews and interview whiteboards.

Domain ownership and handoff map

diagram

CPU OWNERSHIP LAYERS - Clock/Power Domains (CPU)

artifact area     owner
----------------  ----------------------------
architecture    clock architect
RTL/microarch   low-power architect
software/tools  SoC integration lead

Rule: every regressed metric must map to an explicit owner and closure artifact.

Clock/power crossing debug tree

diagram

ROOT-CAUSE TREE - Clock/Power Domains (CPU)

clock skew budget usage, CDC/RDC violation count, and power-state transition stability regressed
        |
  reproducible on fixed seed?
      /               \
    no                 yes
    |                   |
env/tool drift      first failing stage?
                    /        |        \
                front-end   execute   memory/system
                   |          |            |
              fetch/decode   port/ROB   cache/TLB/NoC

Stop at first confirmed mechanism, then patch with owner accountability.

Out-of-order control map

diagram

OOO CORE BLOCK DIAGRAM - Clock/Power Domains (CPU)

decode -> rename -> dispatch -> reservation stations -> execute units
             |                        |                    |
       free-list / map table       wakeup-select         writeback
             \                        |                    /
              +-------- reorder buffer / retire ---------+

Focus: rename to retire dataflow

Memory hierarchy map

diagram

CPU CACHE + MEMORY HIERARCHY - Clock/Power Domains (CPU)

                 [ L1I ]   [ L1D ]
               32-64KB, ~4 cycles
                      \     /
                       [  L2  ]
                 512KB-2MB, ~12 cycles
                           |
                         [ L3 ]
               shared LLC, 30-60 cycles
                           |
                    [ DDR/HBM memory ]
                    80-150ns effective

Optimization lens: latency vs capacity tradeoff

Speculation lens

diagram

BRANCH PREDICTOR VIEW - Clock/Power Domains (CPU)

fetch PC -> BTB lookup -> direction predictor -> target select -> fetch redirect
               |               |                    |
          BTB miss cost     confidence         RAS / indirect path

branch resolves in execute:
correct prediction  -> pipeline keeps flowing
mispredict          -> flush + restart + refill

Focus: minimize wrong-path work

Ownership layers

diagram

CPU OWNERSHIP LAYERS - Clock/Power Domains (CPU)

artifact area     owner
----------------  ----------------------------
architecture    clock architect
RTL/microarch   low-power architect
software/tools  SoC integration lead

Rule: every regressed metric must map to an explicit owner and closure artifact.

Evidence required

Primary metric: clock skew budget usage, CDC/RDC violation count, and power-state transition stability.
Primary artifact: clock tree partition map, UPF/CPF intent review, and CDC-RDC signoff report.
Owners to include: clock architect, low-power architect, SoC integration lead.
One reproducible failing workload and one stable comparator run.
One run with fully locked environment metadata for causal comparison.

Compute-memory limit lens

diagram

CPU ROOFLINE - Clock/Power Domains (CPU)

performance
   ^
   |                 compute roof
   |                /
   |               /
   |--------------/---------------- memory roof
   +----------------------------------------------> arithmetic intensity
      memory-bound                 compute-bound

Interpretation: separate compute and memory limits

Key takeaways

Classify stage loss before proposing fixes.
Use artifacts to separate mechanism from symptoms.
Close with owner accountability and rollback criteria.

Common pitfalls

Using average IPC alone while ignoring tail behavior.
Comparing traces across mismatched binaries or thermal states.
Calling closure without workload-level validation.

CPU deep dive

Physical closure and observability planning determine whether CPU architecture wins survive first silicon.

Concept diagram

diagram

CPU SILICON CLOSURE

core/LLC floorplan -> clock/power domains -> PMCs/observability -> bring-up

Metric graph

diagram

CLOSURE RISK MIX

timing margin risk   █████
thermal hotspots     ████
bring-up blockers    ███

Reports and artifacts

floorplan congestion map
timing closure summary
IR/thermal transient report
bring-up milestone tracker

Mini case study

A floorplan change improved routing congestion but created thermal clustering that forced frequency throttling in sustained tests.

Debug branches

Trace critical paths to physical regions and domain crossings
Run dynamic IR and thermal checks on burst workloads
Use PMCs and bring-up logs to correlate silicon symptoms to design intent

Senior review question

Ask: which CPI/latency evidence proves this topic is truly closed beyond synthetic benchmarks?

Key takeaways

Always connect microarchitectural counter changes to product workload outcomes.
Lock binary, compiler, firmware, and thermal metadata before comparing CPU traces.

Common pitfalls

Treating average IPC as sufficient proof while ignoring latency tails and outliers.
Applying predictor or prefetch tweaks without first-failing-stage attribution.
Declaring closure without reproducible perf, correctness, and power gates.

Practice this lesson