CPU Design · All levels

Core Array Floorplanning

Physical Design, Perf & Bring-up: Core clusters, LLC slices, and interconnect macros must be placed for routability and locality; poor macro adjacency increases delay, congestion, and closure churn.

What this topic teaches

Core Array Floorplanning turns CPU design theory into actionable review decisions. Core clusters, LLC slices, and interconnect macros must be placed for routability and locality; poor macro adjacency increases delay, congestion, and closure churn. The target is evidence-backed closure, not opinion-driven tuning.

Senior-engineer framing question

When wirelength congestion index, macro adjacency quality, and frequency headroom shifts, can you prove first failing stage, dominant mechanism, accountable owner, and release-safe mitigation?

diagram

CPU PIPELINE VIEW - Core Array Floorplanning

fetch -> decode -> rename -> dispatch -> execute -> retire
  |        |         |          |         |         |
icache   uop flow   map table  queueing  FU ports  ROB commit

steady-state goal:
keep every stage supplied without bubbles or flush storms

Focus: connect metric movement to the first stage loss
Metric tracked: wirelength congestion index, macro adjacency quality, and frequency headroom

Architecture visuals

Draw the mechanism before changing knobs. These visuals are optimized for design reviews and interview whiteboards.

Floorplan ownership and closure lanes

diagram

CPU OWNERSHIP LAYERS - Core Array Floorplanning

artifact area     owner
----------------  ----------------------------
architecture    physical design lead
RTL/microarch   CPU architect
software/tools  implementation owner

Rule: every regressed metric must map to an explicit owner and closure artifact.

Floorplan optimization trajectory

diagram

BEFORE / AFTER TREND - Core Array Floorplanning

metric quality
  ^
  |                        o target region
  |                 o post-fix rerun
  |            o
  |      o baseline (failing)
  +----------------------------------------------> iteration
      capture       isolate mechanism       close

Use this to prove improvement is causal and stable.

Out-of-order control map

diagram

OOO CORE BLOCK DIAGRAM - Core Array Floorplanning

decode -> rename -> dispatch -> reservation stations -> execute units
             |                        |                    |
       free-list / map table       wakeup-select         writeback
             \                        |                    /
              +-------- reorder buffer / retire ---------+

Focus: rename to retire dataflow

Memory hierarchy map

diagram

CPU CACHE + MEMORY HIERARCHY - Core Array Floorplanning

                 [ L1I ]   [ L1D ]
               32-64KB, ~4 cycles
                      \     /
                       [  L2  ]
                 512KB-2MB, ~12 cycles
                           |
                         [ L3 ]
               shared LLC, 30-60 cycles
                           |
                    [ DDR/HBM memory ]
                    80-150ns effective

Optimization lens: latency vs capacity tradeoff

Speculation lens

diagram

BRANCH PREDICTOR VIEW - Core Array Floorplanning

fetch PC -> BTB lookup -> direction predictor -> target select -> fetch redirect
               |               |                    |
          BTB miss cost     confidence         RAS / indirect path

branch resolves in execute:
correct prediction  -> pipeline keeps flowing
mispredict          -> flush + restart + refill

Focus: minimize wrong-path work

Ownership layers

diagram

CPU OWNERSHIP LAYERS - Core Array Floorplanning

artifact area     owner
----------------  ----------------------------
architecture    physical design lead
RTL/microarch   CPU architect
software/tools  implementation owner

Rule: every regressed metric must map to an explicit owner and closure artifact.

Evidence required

Primary metric: wirelength congestion index, macro adjacency quality, and frequency headroom.
Primary artifact: floorplan snapshot, congestion heatmap, and timing path locality report.
Owners to include: physical design lead, CPU architect, implementation owner.
One reproducible failing workload and one stable comparator run.
One run with fully locked environment metadata for causal comparison.

Compute-memory limit lens

diagram

CPU ROOFLINE - Core Array Floorplanning

performance
   ^
   |                 compute roof
   |                /
   |               /
   |--------------/---------------- memory roof
   +----------------------------------------------> arithmetic intensity
      memory-bound                 compute-bound

Interpretation: separate compute and memory limits

Key takeaways

Classify stage loss before proposing fixes.
Use artifacts to separate mechanism from symptoms.
Close with owner accountability and rollback criteria.

Common pitfalls

Using average IPC alone while ignoring tail behavior.
Comparing traces across mismatched binaries or thermal states.
Calling closure without workload-level validation.

CPU deep dive

Physical closure and observability planning determine whether CPU architecture wins survive first silicon.

Concept diagram

diagram

CPU SILICON CLOSURE

core/LLC floorplan -> clock/power domains -> PMCs/observability -> bring-up

Metric graph

diagram

CLOSURE RISK MIX

timing margin risk   █████
thermal hotspots     ████
bring-up blockers    ███

Reports and artifacts

floorplan congestion map
timing closure summary
IR/thermal transient report
bring-up milestone tracker

Mini case study

A floorplan change improved routing congestion but created thermal clustering that forced frequency throttling in sustained tests.

Debug branches

Trace critical paths to physical regions and domain crossings
Run dynamic IR and thermal checks on burst workloads
Use PMCs and bring-up logs to correlate silicon symptoms to design intent

Senior review question

Ask: which CPI/latency evidence proves this topic is truly closed beyond synthetic benchmarks?

Key takeaways

Always connect microarchitectural counter changes to product workload outcomes.
Lock binary, compiler, firmware, and thermal metadata before comparing CPU traces.

Common pitfalls

Treating average IPC as sufficient proof while ignoring latency tails and outliers.
Applying predictor or prefetch tweaks without first-failing-stage attribution.
Declaring closure without reproducible perf, correctness, and power gates.

Practice this lesson