CPU Design · All levels

Performance Counters (PMC)

Physical Design, Perf & Bring-up: PMCs expose stall classes and throughput limits; the value comes from event taxonomy quality, synchronized sampling, and disciplined correlation against workload traces.

What this topic teaches

Performance Counters (PMC) turns CPU design theory into actionable review decisions. PMCs expose stall classes and throughput limits; the value comes from event taxonomy quality, synchronized sampling, and disciplined correlation against workload traces. The target is evidence-backed closure, not opinion-driven tuning.

Senior-engineer framing question

When counter fidelity, sampling overhead, and triage turnaround time shifts, can you prove first failing stage, dominant mechanism, accountable owner, and release-safe mitigation?

diagram

CPU PIPELINE VIEW - Performance Counters (PMC)

fetch -> decode -> rename -> dispatch -> execute -> retire
  |        |         |          |         |         |
icache   uop flow   map table  queueing  FU ports  ROB commit

steady-state goal:
keep every stage supplied without bubbles or flush storms

Focus: connect metric movement to the first stage loss
Metric tracked: counter fidelity, sampling overhead, and triage turnaround time

Architecture visuals

Draw the mechanism before changing knobs. These visuals are optimized for design reviews and interview whiteboards.

Counter-guided closure trend

diagram

BEFORE / AFTER TREND - Performance Counters (PMC)

metric quality
  ^
  |                        o target region
  |                 o post-fix rerun
  |            o
  |      o baseline (failing)
  +----------------------------------------------> iteration
      capture       isolate mechanism       close

Use this to prove improvement is causal and stable.

PMC anomaly triage tree

diagram

ROOT-CAUSE TREE - Performance Counters (PMC)

counter fidelity, sampling overhead, and triage turnaround time regressed
        |
  reproducible on fixed seed?
      /               \
    no                 yes
    |                   |
env/tool drift      first failing stage?
                    /        |        \
                front-end   execute   memory/system
                   |          |            |
              fetch/decode   port/ROB   cache/TLB/NoC

Stop at first confirmed mechanism, then patch with owner accountability.

Out-of-order control map

diagram

OOO CORE BLOCK DIAGRAM - Performance Counters (PMC)

decode -> rename -> dispatch -> reservation stations -> execute units
             |                        |                    |
       free-list / map table       wakeup-select         writeback
             \                        |                    /
              +-------- reorder buffer / retire ---------+

Focus: rename to retire dataflow

Memory hierarchy map

diagram

CPU CACHE + MEMORY HIERARCHY - Performance Counters (PMC)

                 [ L1I ]   [ L1D ]
               32-64KB, ~4 cycles
                      \     /
                       [  L2  ]
                 512KB-2MB, ~12 cycles
                           |
                         [ L3 ]
               shared LLC, 30-60 cycles
                           |
                    [ DDR/HBM memory ]
                    80-150ns effective

Optimization lens: latency vs capacity tradeoff

Speculation lens

diagram

BRANCH PREDICTOR VIEW - Performance Counters (PMC)

fetch PC -> BTB lookup -> direction predictor -> target select -> fetch redirect
               |               |                    |
          BTB miss cost     confidence         RAS / indirect path

branch resolves in execute:
correct prediction  -> pipeline keeps flowing
mispredict          -> flush + restart + refill

Focus: minimize wrong-path work

Ownership layers

diagram

CPU OWNERSHIP LAYERS - Performance Counters (PMC)

artifact area     owner
----------------  ----------------------------
architecture    silicon performance lead
RTL/microarch   firmware owner
software/tools  tooling owner

Rule: every regressed metric must map to an explicit owner and closure artifact.

Evidence required

Primary metric: counter fidelity, sampling overhead, and triage turnaround time.
Primary artifact: PMU event map, counter correlation notebook, and anomaly triage report.
Owners to include: silicon performance lead, firmware owner, tooling owner.
One reproducible failing workload and one stable comparator run.
One run with fully locked environment metadata for causal comparison.

Compute-memory limit lens

diagram

CPU ROOFLINE - Performance Counters (PMC)

performance
   ^
   |                 compute roof
   |                /
   |               /
   |--------------/---------------- memory roof
   +----------------------------------------------> arithmetic intensity
      memory-bound                 compute-bound

Interpretation: separate compute and memory limits

Key takeaways

Classify stage loss before proposing fixes.
Use artifacts to separate mechanism from symptoms.
Close with owner accountability and rollback criteria.

Common pitfalls

Using average IPC alone while ignoring tail behavior.
Comparing traces across mismatched binaries or thermal states.
Calling closure without workload-level validation.

CPU deep dive

Physical closure and observability planning determine whether CPU architecture wins survive first silicon.

Concept diagram

diagram

CPU SILICON CLOSURE

core/LLC floorplan -> clock/power domains -> PMCs/observability -> bring-up

Metric graph

diagram

CLOSURE RISK MIX

timing margin risk   █████
thermal hotspots     ████
bring-up blockers    ███

Reports and artifacts

floorplan congestion map
timing closure summary
IR/thermal transient report
bring-up milestone tracker

Mini case study

A floorplan change improved routing congestion but created thermal clustering that forced frequency throttling in sustained tests.

Debug branches

Trace critical paths to physical regions and domain crossings
Run dynamic IR and thermal checks on burst workloads
Use PMCs and bring-up logs to correlate silicon symptoms to design intent

Senior review question

Ask: which CPI/latency evidence proves this topic is truly closed beyond synthetic benchmarks?

Key takeaways

Always connect microarchitectural counter changes to product workload outcomes.
Lock binary, compiler, firmware, and thermal metadata before comparing CPU traces.

Common pitfalls

Treating average IPC as sufficient proof while ignoring latency tails and outliers.
Applying predictor or prefetch tweaks without first-failing-stage attribution.
Declaring closure without reproducible perf, correctness, and power gates.

Practice this lesson