Execution Units & Pipelines

Section goal

Integer, floating-point, vector, and memory execution datapaths that determine peak throughput and hazard behavior.

How to study this section

1. Start with each topic hub to establish mechanism-first framing.

2. Use reports and debug pages to separate symptoms from root cause.

3. Practice worked examples and interview drills under fixed metadata.

4. Close with checklist and silicon impact before signoff claims.

Topics

1. integer-alu-pipelines/ - Integer ALU Pipelines

2. fpu-and-vector-units/ - FPU and Vector Units

3. load-store-queue/ - Load Store Queue

4. multi-issue-and-port-conflicts/ - Multi-Issue and Port Conflicts

Related topics

• CPU Design course hub

CPU deep dive

Execution throughput depends on port balance, bypass quality, and realistic instruction mix assumptions.

Concept diagram

EXECUTION DATAPATH

issue -> ALU/FPU/vector/LSQ ports -> writeback -> retire

Metric graph

EXECUTION LOSS DRIVERS

port conflicts      █████
bypass hazards      ████
LSQ ordering stalls ███

Reports and artifacts

• port pressure heatmap

• pipeline hazard report

• ALU/FPU/vector utilization split

• LSQ ordering diagnostics

Mini case study

A compiler scheduling update over-concentrated uops on one port class, reducing effective multi-issue throughput.

Debug branches

• Map instruction classes to port availability

• Validate forwarding depth against dependency chains

• Inspect LSQ ordering events before widening pipes

Senior review question

Ask: which CPI/latency evidence proves this topic is truly closed beyond synthetic benchmarks?