CPU Design · All levels

Load Store Queue

Execution Units & Pipelines: The LSQ tracks in-flight memory ops, enforces ordering constraints, and enables forwarding from younger stores to dependent loads when addresses match safely.

What this topic teaches

Load Store Queue turns CPU design theory into actionable review decisions. The LSQ tracks in-flight memory ops, enforces ordering constraints, and enables forwarding from younger stores to dependent loads when addresses match safely. The target is evidence-backed closure, not opinion-driven tuning.

Senior-engineer framing question

When LSQ occupancy, memory ordering violation rate, and store-forwarding hit ratio shifts, can you prove first failing stage, dominant mechanism, accountable owner, and release-safe mitigation?

diagram

CPU PIPELINE VIEW - Load Store Queue

fetch -> decode -> rename -> dispatch -> execute -> retire
  |        |         |          |         |         |
icache   uop flow   map table  queueing  FU ports  ROB commit

steady-state goal:
keep every stage supplied without bubbles or flush storms

Focus: connect metric movement to the first stage loss
Metric tracked: LSQ occupancy, memory ordering violation rate, and store-forwarding hit ratio

Architecture visuals

Draw the mechanism before changing knobs. These visuals are optimized for design reviews and interview whiteboards.

LSQ ordering and forwarding path

diagram

OOO CORE BLOCK DIAGRAM - Load Store Queue

decode -> rename -> dispatch -> reservation stations -> execute units
             |                        |                    |
       free-list / map table       wakeup-select         writeback
             \                        |                    /
              +-------- reorder buffer / retire ---------+

Focus: trace load/store issue, address check, and store-forward resolution

LSQ miss impact in hierarchy

diagram

CPU CACHE + MEMORY HIERARCHY - Load Store Queue

                 [ L1I ]   [ L1D ]
               32-64KB, ~4 cycles
                      \     /
                       [  L2  ]
                 512KB-2MB, ~12 cycles
                           |
                         [ L3 ]
               shared LLC, 30-60 cycles
                           |
                    [ DDR/HBM memory ]
                    80-150ns effective

Optimization lens: map unresolved LSQ accesses into cache and DRAM latency stack

Out-of-order control map

diagram

OOO CORE BLOCK DIAGRAM - Load Store Queue

decode -> rename -> dispatch -> reservation stations -> execute units
             |                        |                    |
       free-list / map table       wakeup-select         writeback
             \                        |                    /
              +-------- reorder buffer / retire ---------+

Focus: rename to retire dataflow

Memory hierarchy map

diagram

CPU CACHE + MEMORY HIERARCHY - Load Store Queue

                 [ L1I ]   [ L1D ]
               32-64KB, ~4 cycles
                      \     /
                       [  L2  ]
                 512KB-2MB, ~12 cycles
                           |
                         [ L3 ]
               shared LLC, 30-60 cycles
                           |
                    [ DDR/HBM memory ]
                    80-150ns effective

Optimization lens: latency vs capacity tradeoff

Speculation lens

diagram

BRANCH PREDICTOR VIEW - Load Store Queue

fetch PC -> BTB lookup -> direction predictor -> target select -> fetch redirect
               |               |                    |
          BTB miss cost     confidence         RAS / indirect path

branch resolves in execute:
correct prediction  -> pipeline keeps flowing
mispredict          -> flush + restart + refill

Focus: minimize wrong-path work

Ownership layers

diagram

CPU OWNERSHIP LAYERS - Load Store Queue

artifact area     owner
----------------  ----------------------------
architecture    memory ordering owner
RTL/microarch   LSQ RTL owner
software/tools  verification owner

Rule: every regressed metric must map to an explicit owner and closure artifact.

Evidence required

Primary metric: LSQ occupancy, memory ordering violation rate, and store-forwarding hit ratio.
Primary artifact: LSQ timeline, forwarding mismatch log, and memory dependence report.
Owners to include: memory ordering owner, LSQ RTL owner, verification owner.
One reproducible failing workload and one stable comparator run.
One run with fully locked environment metadata for causal comparison.

Compute-memory limit lens

diagram

CPU ROOFLINE - Load Store Queue

performance
   ^
   |                 compute roof
   |                /
   |               /
   |--------------/---------------- memory roof
   +----------------------------------------------> arithmetic intensity
      memory-bound                 compute-bound

Interpretation: separate compute and memory limits

Key takeaways

Classify stage loss before proposing fixes.
Use artifacts to separate mechanism from symptoms.
Close with owner accountability and rollback criteria.

Common pitfalls

Using average IPC alone while ignoring tail behavior.
Comparing traces across mismatched binaries or thermal states.
Calling closure without workload-level validation.

CPU deep dive

Execution throughput depends on port balance, bypass quality, and realistic instruction mix assumptions.

Concept diagram

diagram

EXECUTION DATAPATH

issue -> ALU/FPU/vector/LSQ ports -> writeback -> retire

Metric graph

diagram

EXECUTION LOSS DRIVERS

port conflicts      █████
bypass hazards      ████
LSQ ordering stalls ███

Reports and artifacts

port pressure heatmap
pipeline hazard report
ALU/FPU/vector utilization split
LSQ ordering diagnostics

Mini case study

A compiler scheduling update over-concentrated uops on one port class, reducing effective multi-issue throughput.

Debug branches

Map instruction classes to port availability
Validate forwarding depth against dependency chains
Inspect LSQ ordering events before widening pipes

Senior review question

Ask: which CPI/latency evidence proves this topic is truly closed beyond synthetic benchmarks?

Key takeaways

Always connect microarchitectural counter changes to product workload outcomes.
Lock binary, compiler, firmware, and thermal metadata before comparing CPU traces.

Common pitfalls

Treating average IPC as sufficient proof while ignoring latency tails and outliers.
Applying predictor or prefetch tweaks without first-failing-stage attribution.
Declaring closure without reproducible perf, correctness, and power gates.

Practice this lesson