Load Store Queue: Debug Playbook

Debug playbook

Debug Playbook for Load Store Queue centers on LSQ occupancy, memory ordering violation rate, and store-forwarding hit ratio. Tie every claim to a measurable artifact and an owner-controlled action.

1. Freeze workload seed, binary, compiler, firmware, and thermal setup.

2. Find first persistent stage loss in timeline.

3. Build one reduced reproducer for dominant hypothesis.

4. Patch minimal fix with explicit rollback gate.

5. Re-run full correctness + performance + power matrix.

Debug decision tree

ROOT-CAUSE TREE - Load Store Queue

LSQ occupancy, memory ordering violation rate, and store-forwarding hit ratio regressed
        |
  reproducible on fixed seed?
      /               \
    no                 yes
    |                   |
env/tool drift      first failing stage?
                    /        |        \
                front-end   execute   memory/system
                   |          |            |
              fetch/decode   port/ROB   cache/TLB/NoC

Stop at first confirmed mechanism, then patch with owner accountability.

Review memo template

CPU DESIGN REVIEW MEMO - Execution Units & Pipelines / Load Store Queue

1. Symptom
   - Watched metric: LSQ occupancy, memory ordering violation rate, and store-forwarding hit ratio
   - Failing workload slice: <name>
   - First failing stage: <fetch/decode/rename/execute/memory/system>
   - Revision tags: <binary/compiler/firmware/uarch stepping>

2. Mechanism hypothesis
   - Primary mechanism: The LSQ tracks in-flight memory ops, enforces ordering constraints, and enables forwarding from younger stores to dependent loads when addresses match safely.
   - Competing hypotheses: <front-end, scheduler, memory, coherence, physical limits>
   - Missing evidence: <counter snapshot, trace, topology/thermal map>

3. Proposed action
   - Minimal reversible fix: <uarch policy/compiler/runtime/config>
   - Expected movement: <IPC/CPI/latency tail/perf-per-watt>
   - Regression risk: correctness, power, thermal, software compatibility

4. Signoff
   - Re-run artifact: LSQ timeline, forwarding mismatch log, and memory dependence report
   - Required owners: memory ordering owner, LSQ RTL owner, verification owner
   - Final decision: ship, bounded rollout, rollback, or escalate

CPU deep dive

Execution throughput depends on port balance, bypass quality, and realistic instruction mix assumptions.

Concept diagram

EXECUTION DATAPATH

issue -> ALU/FPU/vector/LSQ ports -> writeback -> retire

Metric graph

EXECUTION LOSS DRIVERS

port conflicts      █████
bypass hazards      ████
LSQ ordering stalls ███

Reports and artifacts

• port pressure heatmap

• pipeline hazard report

• ALU/FPU/vector utilization split

• LSQ ordering diagnostics

Mini case study

A compiler scheduling update over-concentrated uops on one port class, reducing effective multi-issue throughput.

Debug branches

• Map instruction classes to port availability

• Validate forwarding depth against dependency chains

• Inspect LSQ ordering events before widening pipes

Senior review question

Ask: which CPI/latency evidence proves this topic is truly closed beyond synthetic benchmarks?

Key takeaways

• Always connect microarchitectural counter changes to product workload outcomes.

• Lock binary, compiler, firmware, and thermal metadata before comparing CPU traces.

Common pitfalls

• Treating average IPC as sufficient proof while ignoring latency tails and outliers.

• Applying predictor or prefetch tweaks without first-failing-stage attribution.

• Declaring closure without reproducible perf, correctness, and power gates.

Principal CPU review addendum

Load Store Queue should be treated as a system behavior, not an isolated block definition. In a shipping CPU core, ISA intent, front-end delivery, speculation depth, scheduler behavior, memory translation, coherence traffic, and physical limits all interact before software observes final IPC or CPI.

The LSQ tracks in-flight memory ops, enforces ordering constraints, and enables forwarding from younger stores to dependent loads when addresses match safely. CPU teams pay for repeated inefficiency: one extra bubble, one wrong target, one port conflict, or one translation miss pattern can replicate across billions of instructions and dominate product-level latency and energy.

Use LSQ occupancy, memory ordering violation rate, and store-forwarding hit ratio as an investigation start point, not as the conclusion. A counter movement only becomes actionable when paired with workload phase tags, PMU event context, a controlled repro, and artifact evidence such as LSQ timeline, forwarding mismatch log, and memory dependence report.

Execution pipelines deliver value when issue policy, bypassing, and port provisioning match workload instruction mix. Senior review quality comes from proving the full chain: workload request -> microarchitectural response -> measured bottleneck -> smallest owner fix -> regression-safe validation.

Review discipline should force a causal chain: workload shape -> front-end/speculation behavior -> execution/memory pressure -> retire efficiency -> product impact. That chain keeps CPU decisions evidence-driven and owner-accountable.