CPU Design · All levels

NUMA and Memory Affinity

Multicore & System Integration: Thread and page placement policy controls whether cores access local or remote memory; poor affinity silently adds latency and coherence overhead to otherwise efficient software.

What this topic teaches

NUMA and Memory Affinity turns CPU design theory into actionable review decisions. Thread and page placement policy controls whether cores access local or remote memory; poor affinity silently adds latency and coherence overhead to otherwise efficient software. The target is evidence-backed closure, not opinion-driven tuning.

Senior-engineer framing question

When remote memory access ratio, NUMA latency delta, and workload affinity score shifts, can you prove first failing stage, dominant mechanism, accountable owner, and release-safe mitigation?

diagram

CPU PIPELINE VIEW - NUMA and Memory Affinity

fetch -> decode -> rename -> dispatch -> execute -> retire
  |        |         |          |         |         |
icache   uop flow   map table  queueing  FU ports  ROB commit

steady-state goal:
keep every stage supplied without bubbles or flush storms

Focus: connect metric movement to the first stage loss
Metric tracked: remote memory access ratio, NUMA latency delta, and workload affinity score

Architecture visuals

Draw the mechanism before changing knobs. These visuals are optimized for design reviews and interview whiteboards.

Local vs remote memory path lengths

diagram

CPU CACHE + MEMORY HIERARCHY - NUMA and Memory Affinity

                 [ L1I ]   [ L1D ]
               32-64KB, ~4 cycles
                      \     /
                       [  L2  ]
                 512KB-2MB, ~12 cycles
                           |
                         [ L3 ]
               shared LLC, 30-60 cycles
                           |
                    [ DDR/HBM memory ]
                    80-150ns effective

Optimization lens: contrast same-node access against remote-node latency penalties

NUMA locality throughput lens

diagram

CPU ROOFLINE - NUMA and Memory Affinity

performance
   ^
   |                 compute roof
   |                /
   |               /
   |--------------/---------------- memory roof
   +----------------------------------------------> arithmetic intensity
      memory-bound                 compute-bound

Interpretation: illustrate throughput collapse from remote-heavy placement

Out-of-order control map

diagram

OOO CORE BLOCK DIAGRAM - NUMA and Memory Affinity

decode -> rename -> dispatch -> reservation stations -> execute units
             |                        |                    |
       free-list / map table       wakeup-select         writeback
             \                        |                    /
              +-------- reorder buffer / retire ---------+

Focus: rename to retire dataflow

Memory hierarchy map

diagram

CPU CACHE + MEMORY HIERARCHY - NUMA and Memory Affinity

                 [ L1I ]   [ L1D ]
               32-64KB, ~4 cycles
                      \     /
                       [  L2  ]
                 512KB-2MB, ~12 cycles
                           |
                         [ L3 ]
               shared LLC, 30-60 cycles
                           |
                    [ DDR/HBM memory ]
                    80-150ns effective

Optimization lens: latency vs capacity tradeoff

Speculation lens

diagram

BRANCH PREDICTOR VIEW - NUMA and Memory Affinity

fetch PC -> BTB lookup -> direction predictor -> target select -> fetch redirect
               |               |                    |
          BTB miss cost     confidence         RAS / indirect path

branch resolves in execute:
correct prediction  -> pipeline keeps flowing
mispredict          -> flush + restart + refill

Focus: minimize wrong-path work

Ownership layers

diagram

CPU OWNERSHIP LAYERS - NUMA and Memory Affinity

artifact area     owner
----------------  ----------------------------
architecture    system software owner
RTL/microarch   platform architect
software/tools  performance engineer

Rule: every regressed metric must map to an explicit owner and closure artifact.

Evidence required

Primary metric: remote memory access ratio, NUMA latency delta, and workload affinity score.
Primary artifact: NUMA locality profile, page-placement log, and latency percentile report.
Owners to include: system software owner, platform architect, performance engineer.
One reproducible failing workload and one stable comparator run.
One run with fully locked environment metadata for causal comparison.

Compute-memory limit lens

diagram

CPU ROOFLINE - NUMA and Memory Affinity

performance
   ^
   |                 compute roof
   |                /
   |               /
   |--------------/---------------- memory roof
   +----------------------------------------------> arithmetic intensity
      memory-bound                 compute-bound

Interpretation: separate compute and memory limits

Key takeaways

Classify stage loss before proposing fixes.
Use artifacts to separate mechanism from symptoms.
Close with owner accountability and rollback criteria.

Common pitfalls

Using average IPC alone while ignoring tail behavior.
Comparing traces across mismatched binaries or thermal states.
Calling closure without workload-level validation.

CPU deep dive

Scaling across cores is limited by coherence and interconnect behavior before compute saturation on many workloads.

Concept diagram

diagram

MULTICORE SYSTEM VIEW

cores + private caches <-> LLC slices <-> interconnect <-> memory controllers

Metric graph

diagram

SCALING EFFICIENCY

ideal scaling        ███████████
observed under load  ███████
after policy tuning  █████████

Reports and artifacts

coherence traffic matrix
NoC congestion map
NUMA locality profile
synchronization contention report

Mini case study

A lock-heavy service regressed at higher core counts because coherence invalidations and NoC hotspots dominated.

Debug branches

Classify traffic as coherence, demand miss, or synchronization
Measure hotspot links instead of aggregate NoC throughput
Validate thread and page affinity before hardware changes

Senior review question

Ask: which CPI/latency evidence proves this topic is truly closed beyond synthetic benchmarks?

Key takeaways

Always connect microarchitectural counter changes to product workload outcomes.
Lock binary, compiler, firmware, and thermal metadata before comparing CPU traces.

Common pitfalls

Treating average IPC as sufficient proof while ignoring latency tails and outliers.
Applying predictor or prefetch tweaks without first-failing-stage attribution.
Declaring closure without reproducible perf, correctness, and power gates.

Practice this lesson