CPU Design · All levels

Reservation Stations Scheduling

Out-of-Order Execution: Reservation stations hold dispatched uops until operands are ready; wakeup-select timing, tag broadcast load, and arbitration policy decide how effectively ready work reaches execution ports each cycle.

What this topic teaches

Reservation Stations Scheduling turns CPU design theory into actionable review decisions. Reservation stations hold dispatched uops until operands are ready; wakeup-select timing, tag broadcast load, and arbitration policy decide how effectively ready work reaches execution ports each cycle. The target is evidence-backed closure, not opinion-driven tuning.

Senior-engineer framing question

When issue queue occupancy, wakeup-select latency, and scheduler fairness shifts, can you prove first failing stage, dominant mechanism, accountable owner, and release-safe mitigation?

diagram

CPU PIPELINE VIEW - Reservation Stations Scheduling

fetch -> decode -> rename -> dispatch -> execute -> retire
  |        |         |          |         |         |
icache   uop flow   map table  queueing  FU ports  ROB commit

steady-state goal:
keep every stage supplied without bubbles or flush storms

Focus: connect metric movement to the first stage loss
Metric tracked: issue queue occupancy, wakeup-select latency, and scheduler fairness

Architecture visuals

Draw the mechanism before changing knobs. These visuals are optimized for design reviews and interview whiteboards.

Wakeup-select critical loop

diagram

OOO CORE BLOCK DIAGRAM - Reservation Stations Scheduling

decode -> rename -> dispatch -> reservation stations -> execute units
             |                        |                    |
       free-list / map table       wakeup-select         writeback
             \                        |                    /
              +-------- reorder buffer / retire ---------+

Focus: map ready tagging, arbitration, and issue queue pressure at scale

Scheduler-induced bubble map

diagram

CPU PIPELINE VIEW - Reservation Stations Scheduling

fetch -> decode -> rename -> dispatch -> execute -> retire
  |        |         |          |         |         |
icache   uop flow   map table  queueing  FU ports  ROB commit

steady-state goal:
keep every stage supplied without bubbles or flush storms

Focus: show how issue queue inefficiency back-pressures dispatch
Metric tracked: issue queue occupancy, wakeup-select latency, and scheduler fairness

Out-of-order control map

diagram

OOO CORE BLOCK DIAGRAM - Reservation Stations Scheduling

decode -> rename -> dispatch -> reservation stations -> execute units
             |                        |                    |
       free-list / map table       wakeup-select         writeback
             \                        |                    /
              +-------- reorder buffer / retire ---------+

Focus: rename to retire dataflow

Memory hierarchy map

diagram

CPU CACHE + MEMORY HIERARCHY - Reservation Stations Scheduling

                 [ L1I ]   [ L1D ]
               32-64KB, ~4 cycles
                      \     /
                       [  L2  ]
                 512KB-2MB, ~12 cycles
                           |
                         [ L3 ]
               shared LLC, 30-60 cycles
                           |
                    [ DDR/HBM memory ]
                    80-150ns effective

Optimization lens: latency vs capacity tradeoff

Speculation lens

diagram

BRANCH PREDICTOR VIEW - Reservation Stations Scheduling

fetch PC -> BTB lookup -> direction predictor -> target select -> fetch redirect
               |               |                    |
          BTB miss cost     confidence         RAS / indirect path

branch resolves in execute:
correct prediction  -> pipeline keeps flowing
mispredict          -> flush + restart + refill

Focus: minimize wrong-path work

Ownership layers

diagram

CPU OWNERSHIP LAYERS - Reservation Stations Scheduling

artifact area     owner
----------------  ----------------------------
architecture    scheduler RTL owner
RTL/microarch   timing closure owner
software/tools  CPU architect

Rule: every regressed metric must map to an explicit owner and closure artifact.

Evidence required

Primary metric: issue queue occupancy, wakeup-select latency, and scheduler fairness.
Primary artifact: issue queue heatmap, wakeup-select critical-path report, and dispatch stall profile.
Owners to include: scheduler RTL owner, timing closure owner, CPU architect.
One reproducible failing workload and one stable comparator run.
One run with fully locked environment metadata for causal comparison.

Compute-memory limit lens

diagram

CPU ROOFLINE - Reservation Stations Scheduling

performance
   ^
   |                 compute roof
   |                /
   |               /
   |--------------/---------------- memory roof
   +----------------------------------------------> arithmetic intensity
      memory-bound                 compute-bound

Interpretation: separate compute and memory limits

Key takeaways

Classify stage loss before proposing fixes.
Use artifacts to separate mechanism from symptoms.
Close with owner accountability and rollback criteria.

Common pitfalls

Using average IPC alone while ignoring tail behavior.
Comparing traces across mismatched binaries or thermal states.
Calling closure without workload-level validation.

CPU deep dive

OoO gains come from balanced rename, scheduling, and retire machinery rather than deeper buffers alone.

Concept diagram

diagram

OOO CONTROL LOOP

rename -> dispatch -> issue queues -> execute -> ROB retire -> checkpoint recovery

Metric graph

diagram

OOO PRESSURE SHARE

rename stalls        ████
scheduler wait       █████
retire throttles     ███

Reports and artifacts

ROB occupancy history
rename stall attribution
wakeup-select timing report
recovery latency profile

Mini case study

A deeper ROB improved synthetic ILP but increased recovery latency during branch-heavy production traffic.

Debug branches

Track free-list and map-table pressure by phase
Separate scheduler inefficiency from execution-port limits
Measure post-flush recovery slope before and after fixes

Senior review question

Ask: which CPI/latency evidence proves this topic is truly closed beyond synthetic benchmarks?

Key takeaways

Always connect microarchitectural counter changes to product workload outcomes.
Lock binary, compiler, firmware, and thermal metadata before comparing CPU traces.

Common pitfalls

Treating average IPC as sufficient proof while ignoring latency tails and outliers.
Applying predictor or prefetch tweaks without first-failing-stage attribution.
Declaring closure without reproducible perf, correctness, and power gates.

Practice this lesson