DRAM Array Organization

Section goal

Rows, columns, banks, subarrays, mats, row buffers, wordlines, bitlines, and how organization controls latency, bandwidth, energy, and yield.

This section trains how to reason from traffic behavior to DRAM mechanism, then close with owner accountability, reliability gates, and release-safe decisions.

How to study this section

1. Start with each topic hub and draw the mechanism path.

2. Use reports and debug pages to prove causality before tuning.

3. Practice worked examples and interview drills with explicit evidence chains.

4. Close each topic with checklist and silicon impact pages.

Topics

1. rows-columns-and-subarrays/ - Rows, Columns, and Subarray Granularity

2. banks-bank-groups-and-mats/ - Banks, Bank Groups, Mats, and Parallelism Limits

3. row-buffer-locality/ - Row Buffer Locality and Page Policy

4. address-mapping-and-interleaving/ - Address Mapping, Interleaving, and Disturb-Aware Placement

Related topics

• DRAM & Memory Design course hub

DRAM deep dive

Cell-array and subarray organization determines bitline delay, sensing margin, and locality-sensitive energy cost.

Concept diagram

ARRAY ORGANIZATION VIEW

rows x columns -> mats/subarrays -> local sense amps -> global I/O
physical distance shapes timing and energy

Metric graph

ARRAY ACCESS COST SHARE

bitline settle delay   ██████
sense/restore time     █████
global routing overhead ███

Reports and artifacts

• subarray toggle heatmap

• sense-amplifier utilization report

• bitline RC delay audit

• wordline coupling checklist

Mini case study

A dense address remap increased long-bitline activations, creating extra tRCD guardband and persistent tail-latency drift.

Debug branches

• Map hot addresses to mats and subarray boundaries

• Inspect sense-margin behavior under temperature corners

• Evaluate row-mapping changes before voltage retuning

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?