DRAM & Memory Design · All levels

DRAM & Memory Design Cheatsheet

Dense reference for DRAM bottleneck isolation, timing-aware debug, and closure-ready review decisions.

Debug order

diagram

WORKLOAD -> FIRST FAILING TRANSITION -> MECHANISM -> ARTIFACT -> OWNER -> DECISION

ROW STATE: row-hit reuse vs conflict churn
TIMING: tRCD/tRP/tRAS/tFAW legality and hidden dead cycles
QUEUE: fairness, class starvation, and refresh interference
PHY: eye/Vref/skew margin under corner drift
RAS: CE/UE trends, scrub impact, hammer resilience

Questions before proposing a fix

Which traffic slice fails first and how reproducible is it?
Which command/state transition loses first under fixed tags?
Which artifact proves mechanism causality?
Who owns the smallest reversible fix?
What full-matrix validation and rollback rules close risk?

Practice this lesson