Memory Controller Scheduling

Section goal

Request queues, FR-FCFS, QoS, page policies, bank conflicts, refresh scheduling, and system-level latency/bandwidth control.

This section trains how to reason from traffic behavior to DRAM mechanism, then close with owner accountability, reliability gates, and release-safe decisions.

How to study this section

1. Start with each topic hub and draw the mechanism path.

2. Use reports and debug pages to prove causality before tuning.

3. Practice worked examples and interview drills with explicit evidence chains.

4. Close each topic with checklist and silicon impact pages.

Topics

1. request-queues-and-reorder/ - Request Queues, Reorder Windows, and Bank-Level Parallelism

2. fr-fcfs-and-page-policy/ - FR-FCFS, Row-Buffer Locality, and Page Policy Control

3. qos-and-priority-arbitration/ - QoS Classes, Priority Arbitration, and Starvation Boundaries

4. refresh-scheduling-impact/ - Refresh Scheduling Impact on Latency and Bandwidth

Related topics

• DRAM & Memory Design course hub

DRAM deep dive

Controller policy decides whether DRAM serves locality, fairness, and QoS targets simultaneously.

Concept diagram

CONTROLLER SCHEDULING LOOP

request queues -> row-policy + priority -> command issue -> bank state update

Metric graph

QUEUE PRESSURE MIX

row-hit preference bias ██████
aging/fairness pressure █████
QoS override cost       ███

Reports and artifacts

• scheduler policy comparison

• queue age distribution

• starvation/fairness incident report

• QoS latency percentile dashboard

Mini case study

FR-FCFS tuning improved bulk throughput but starved latency-critical traffic until age caps and class quotas were added.

Debug branches

• Measure queue age tails by traffic class

• Separate row-hit gains from fairness regressions

• Stress policy under mixed burst and random streams

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?