QoS Classes, Priority Arbitration, and Starvation Boundaries

What this topic teaches

QoS Classes, Priority Arbitration, and Starvation Boundaries turns DRAM theory into production-grade review decisions. QoS-aware arbitration overlays policy on top of raw efficiency scheduling so critical clients (for example CPU demand fetches, display, or real-time accelerators) get bounded service even when background traffic is heavy. The controller typically uses weighted priority, aging, credit/token buckets, or deadline-aware boosts to pick among ready requests. Pure fixed priority can satisfy critical latency but often starves low-priority flows; pure fairness can miss hard deadlines. Practical designs combine tiers: first enforce hard constraints (deadline/critical window), then apply weighted fairness among remaining contenders, with aging to guarantee eventual service. Arbitration decisions must be synchronized with read/write batching, bus turnaround penalties, and bank availability, otherwise QoS policy can look correct at request level yet fail at command-level execution. End-to-end QoS therefore requires both scheduler logic and upstream traffic shaping: if NoC or cache eviction policy injects pathological bursts, controller-only fixes may be insufficient. Robust implementations validate SLA behavior using adversarial traffic mixes and explicitly monitor tail latency excursions, not just average service rate.

The main objective is to identify where the first loss starts in the memory service path, prove it with reproducible traces, and close with the smallest owner-controlled fix.

Senior DRAM work is less about isolated register tuning and more about cross-layer causality: traffic shape, command stream legality, bank behavior, PHY margin, and field reliability must agree before signoff.

Senior-engineer framing question

When Per-class latency SLA compliance (real-time, interactive, best-effort) and fairness index under stress traffic. regresses, can you prove whether the first failure is locality collapse, timing-window pressure, scheduler fairness loss, lane-margin drift, or reliability policy overhead?

DRAM CELL DIAGRAM - QoS Classes, Priority Arbitration, and Starvation Boundaries

                bitline (BL)
                    |
           +--------+--------+
wordline --| access transistor|-- storage capacitor (Ccell)
           +--------+--------+
                    |
                  ground

Read:   BL precharge -> WL on -> tiny delta-V -> sense amp amplifies
Write:  drive BL -> WL on -> charge/discharge Ccell -> WL off

Focus: link physical state changes to service-level latency and bandwidth outcomes
Metric tracked: Per-class latency SLA compliance (real-time, interactive, best-effort) and fairness index under stress traffic.

Architecture and timing visuals

Draw the mechanism before tuning knobs. These visuals are optimized for design reviews, bring-up triage, and interview whiteboards.

Scheduler queue pipeline (Qos And Priority Arbitration)

MEMORY CONTROLLER REQUEST PIPELINE

Ingress -> classify(addr,map,dir,class) -> enqueue -> pick -> command issue
              |                              |
              |                              +-- reorder window (N entries)
              |
              +-- queues:
                    [HiPri RQ]  [BestEffort RQ]  [WriteQ]
                         |             |           |
                         +------ arbitration ------+
                                       |
                               legal-if timing wheel passes

FR-FCFS selection with bank states (Qos And Priority Arbitration)

FR-FCFS DECISION VIEW (simplified)

Bank state table:
Bank0: open row 120  ready-for-CAS at t=42
Bank1: open row 087  row-miss for reqX (needs PRE+ACT)
Bank2: idle          can ACT at t=40

Queue head candidates:
reqA -> Bank1 row-miss (oldest)
reqB -> Bank0 row-hit  (younger, ready now)
reqC -> Bank2 row-miss

Pick rule:
1) First-ready wins (reqB now)
2) Among ready ties, oldest first
3) Aging/QoS guard prevents indefinite starvation

QoS + refresh-aware arbitration (Qos And Priority Arbitration)

ARBITRATION TIMELINE WITH REFRESH

time ---> --------------------------------------------------------------->
HiPri class     H1 ---- H2 -- H3 ----------- H4 ----
BestEffort      B1 - B2 ---- B3 ---- B4 ---- B5 ----
Refresh need          r_due..................(deadline)
Scheduler       serve H, then opportunistic B, insert REF before violation

Policy layers:
1) Hard safety: refresh/retention deadlines always met.
2) SLA tiering: critical traffic latency bounds.
3) Fairness/aging: lower classes eventually drain.

Array hierarchy context

ARRAY HIERARCHY MAP - QoS Classes, Priority Arbitration, and Starvation Boundaries

[Channel]
   |
[DIMM/Package]
   |
[Rank]
   |
[Bank Group]
   |
[Bank]
   |
[Subarray]
   |
[Row + Column Decode]
   |
[Cell Mat + Sense Amps]

Lens: map locality decisions to activate/precharge cost.

Command timing context

COMMAND TIMING DIAGRAM - QoS Classes, Priority Arbitration, and Starvation Boundaries

time --->    t0      t1      t2      t3      t4      t5
cmd bus   |  ACT  |   RD  |   WR  |  PRE  |  REF  |  ACT
row state | open  | open  | open  | close | all   | open

key checks:
- ACT->RD >= tRCD
- RD data return >= CL
- WR->PRE >= tWR
- PRE->ACT >= tRP

Controller queue context

CONTROLLER QUEUE VIEW - QoS Classes, Priority Arbitration, and Starvation Boundaries

read queue : [R12 bank0 row88] [R13 bank2 row88] [R14 bank0 row12]
write queue: [W44 bank3 row90] [W45 bank3 row90]

scheduler tick:
1) prioritize ready row hits
2) cap write-drain burst
3) age outstanding reads

issue stream:
cycle 40 -> RD bank0 row88 (hit)
cycle 41 -> RD bank2 row88 (parallel bank group)
cycle 42 -> ACT bank0 row12 (miss prepare)

Ownership layers

MEMORY OWNERSHIP LAYERS - QoS Classes, Priority Arbitration, and Starvation Boundaries

artifact area     owner
----------------  ----------------------------
architecture    memory controller architect
controller FW   SoC QoS architect
verification    NoC owner
silicon bringup firmware power/performance owner

Rule: every signoff metric has a named accountable owner.

Evidence to collect before changing knobs

Fast closure comes from complete evidence packets, not from isolated counter wins. Every recommendation should carry a metric, artifact, owner, and rollback-safe validation plan.

• Primary metric: Per-class latency SLA compliance (real-time, interactive, best-effort) and fairness index under stress traffic..

• Primary artifact: QoS compliance dashboard with per-class SLA miss counters, arbitration decision logs, and starvation watchdog events..

• Owners to include: memory controller architect, SoC QoS architect, NoC owner, firmware power/performance owner, silicon validation owner.

• One reproducible failing traffic slice plus one stable comparator capture.

• One command legality timeline that isolates first failing transition.

• One margin or reliability packet when PHY or RAS behavior is implicated.

Bandwidth-latency operating lens

BANDWIDTH vs LATENCY CURVE - QoS Classes, Priority Arbitration, and Starvation Boundaries

latency
  ^
  |  low-load region
  |      *
  |        *
  |          *
  |            *         knee
  |              *      *
  |                *   *
  |                  ***
  +----------------------------------------------> bandwidth demand
     stable QoS          queue growth / saturation

Use the knee to set safe operating headroom.

Root-cause decision tree

ROOT CAUSE TREE - QoS Classes, Priority Arbitration, and Starvation Boundaries

Per-class latency SLA compliance (real-time, interactive, best-effort) and fairness index under stress traffic. regressed
        |
reproducible with fixed seed?
      /               \
    no                 yes
    |                   |
testbench noise    localize bottleneck
                    /              \
               command path       data path
                 |                  |
             scheduler/FSM      PHY/timing/noise
                 |                  |
             timing limits      training/calibration

Stop at first failing mechanism, then patch and re-measure.

Key takeaways

• Prove first failing transition before touching broad tuning policies.

• Tie command-level behavior to application-visible QoS outcomes.

• Close with accountable owner, rollback criteria, and corner validation.

Common pitfalls

• Optimizing average GB/s while p99 latency and fairness degrade.

• Comparing traces without fixed firmware, timing profile, and thermal tags.

• Declaring closure without reliability and retrain robustness checks.

DRAM deep dive

Controller policy decides whether DRAM serves locality, fairness, and QoS targets simultaneously.

Concept diagram

CONTROLLER SCHEDULING LOOP

request queues -> row-policy + priority -> command issue -> bank state update

Metric graph

QUEUE PRESSURE MIX

row-hit preference bias ██████
aging/fairness pressure █████
QoS override cost       ███

Reports and artifacts

• scheduler policy comparison

• queue age distribution

• starvation/fairness incident report

• QoS latency percentile dashboard

Mini case study

FR-FCFS tuning improved bulk throughput but starved latency-critical traffic until age caps and class quotas were added.

Debug branches

• Measure queue age tails by traffic class

• Separate row-hit gains from fairness regressions

• Stress policy under mixed burst and random streams

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?

Key takeaways

• Always tie controller and PHY counter shifts to application latency and throughput outcomes.

• Lock firmware timing profile, thermal condition, and DIMM state before comparing DRAM captures.

Common pitfalls

• Chasing peak bandwidth while ignoring p99 latency and fairness tails.

• Changing timing guardbands without separating SI noise from scheduling issues.

• Declaring closure without reliability gates, fault injection, and regression replay.