DRAM & Memory Design · All levels

QoS Classes, Priority Arbitration, and Starvation Boundaries: Reports and Metrics

Reports and Metrics for QoS Classes, Priority Arbitration, and Starvation Boundaries.

Reports and metrics

Reports and Metrics for QoS Classes, Priority Arbitration, and Starvation Boundaries focuses on Per-class latency SLA compliance (real-time, interactive, best-effort) and fairness index under stress traffic.. The purpose is to turn memory observations into mechanism-backed actions with explicit owners and release-safe validation.

Reports should explain why Per-class latency SLA compliance (real-time, interactive, best-effort) and fairness index under stress traffic. moved, not simply that it moved. Require evidence that links the movement to command behavior, queue policy, PHY margin, or reliability controls.

Before/after trend

diagram
BEFORE / AFTER GRAPH - QoS Classes, Priority Arbitration, and Starvation Boundaries

metric quality
  ^
  |                       o target band
  |                o post-fix sweep
  |           o
  |      o baseline (failing)
  +----------------------------------------------> iteration
      evidence capture   fix applied   closure run

Use this view to prove improvement is causal, not accidental.

Evidence matrix

diagram
DRAM EVIDENCE MATRIX - QoS Classes, Priority Arbitration, and Starvation Boundaries

+-------------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence                      | Tells you                      | Does not prove                 | Next action               |
+-------------------------------+--------------------------------+--------------------------------+---------------------------+
| row-hit/miss + ACT/PRE mix    | locality and row-state cost    | lane-level capture integrity   | inspect training margins  |
| queue age + class breakdown   | fairness and starvation risk   | command legality details       | parse command timeline    |
| JEDEC legality + bus timeline | timing-window pressure         | root cause by itself           | correlate with traffic map|
| eye / Vref / skew snapshots   | PHY margin and drift behavior  | controller policy quality      | pair with schedule logs   |
| CE/UE + scrub telemetry       | reliability trajectory         | immediate perf bottleneck only | map to hotspot addresses  |
+-------------------------------+--------------------------------+--------------------------------+---------------------------+
  • Track p50/p95/p99 latency and effective bandwidth together.

  • Include command and queue context alongside high-level counters.

  • Tag reports with firmware, timing profile, and thermal state.

  • Call out contradictory evidence instead of hiding it.

DRAM deep dive

Controller policy decides whether DRAM serves locality, fairness, and QoS targets simultaneously.

Concept diagram

diagram
CONTROLLER SCHEDULING LOOP

request queues -> row-policy + priority -> command issue -> bank state update

Metric graph

diagram
QUEUE PRESSURE MIX

row-hit preference bias ██████
aging/fairness pressure █████
QoS override cost       ███

Reports and artifacts

  • scheduler policy comparison

  • queue age distribution

  • starvation/fairness incident report

  • QoS latency percentile dashboard

Mini case study

FR-FCFS tuning improved bulk throughput but starved latency-critical traffic until age caps and class quotas were added.

Debug branches

  • Measure queue age tails by traffic class

  • Separate row-hit gains from fairness regressions

  • Stress policy under mixed burst and random streams

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?

Key takeaways

  • Always tie controller and PHY counter shifts to application latency and throughput outcomes.

  • Lock firmware timing profile, thermal condition, and DIMM state before comparing DRAM captures.

Common pitfalls

  • Chasing peak bandwidth while ignoring p99 latency and fairness tails.

  • Changing timing guardbands without separating SI noise from scheduling issues.

  • Declaring closure without reliability gates, fault injection, and regression replay.

Report interpretation

QoS-aware arbitration overlays policy on top of raw efficiency scheduling so critical clients (for example CPU demand fetches, display, or real-time accelerators) get bounded service even when background traffic is heavy. The controller typically uses weighted priority, aging, credit/token buckets, or deadline-aware boosts to pick among ready requests. Pure fixed priority can satisfy critical latency but often starves low-priority flows; pure fairness can miss hard deadlines. Practical designs combine tiers: first enforce hard constraints (deadline/critical window), then apply weighted fairness among remaining contenders, with aging to guarantee eventual service. Arbitration decisions must be synchronized with read/write batching, bus turnaround penalties, and bank availability, otherwise QoS policy can look correct at request level yet fail at command-level execution. End-to-end QoS therefore requires both scheduler logic and upstream traffic shaping: if NoC or cache eviction policy injects pathological bursts, controller-only fixes may be insufficient. Robust implementations validate SLA behavior using adversarial traffic mixes and explicitly monitor tail latency excursions, not just average service rate. DRAM inefficiency is multiplicative: one extra ACTIVATE, one unnecessary turnaround, one weak lane margin, or one refresh collision repeated across billions of accesses can dominate product tail latency and power.

Use Per-class latency SLA compliance (real-time, interactive, best-effort) and fairness index under stress traffic. as the opening signal, not the conclusion. A metric move only becomes actionable when paired with workload context, command traces, training telemetry, and evidence artifacts such as QoS compliance dashboard with per-class SLA miss counters, arbitration decision logs, and starvation watchdog events..

Memory-controller quality is measured by throughput and tail predictability under mixed traffic, not average bandwidth alone. Senior review quality comes from proving a complete chain: request pattern -> memory-state transition -> bottleneck mechanism -> smallest owner fix -> regression-safe validation.

For QoS Classes, Priority Arbitration, and Starvation Boundaries, reports should explain why Per-class latency SLA compliance (real-time, interactive, best-effort) and fairness index under stress traffic. moved: fewer row misses, lower turnaround waste, better refresh placement, or stronger lane margin stability.

Strong reports include consistency checks: scheduler narrative matches command logs; PHY narrative matches margin sweeps; reliability narrative matches CE/UE trajectories.