Request Queues, Reorder Windows, and Bank-Level Parallelism: Debug Playbook

Debug playbook

Debug Playbook for Request Queues, Reorder Windows, and Bank-Level Parallelism focuses on P95/P99 memory access latency versus sustained bandwidth under mixed read/write traffic.. The purpose is to turn memory observations into mechanism-backed actions with explicit owners and release-safe validation.

DRAM debug should narrow from broad symptom to one dominant mechanism. Avoid mixed-knob sweeps that produce accidental wins without causal confidence.

1. Freeze workload seed, firmware image, timing profile, and thermal setup.

2. Find first failing transition in command timeline.

3. Classify mechanism: locality loss, legality pressure, queue policy, margin drift, or RAS behavior.

4. Build focused reproducer for top hypothesis.

5. Apply minimal reversible fix and define rollback gate.

6. Re-run full performance + reliability matrix.

Debug decision tree

ROOT CAUSE TREE - Request Queues, Reorder Windows, and Bank-Level Parallelism

P95/P99 memory access latency versus sustained bandwidth under mixed read/write traffic. regressed
        |
reproducible with fixed seed?
      /               \
    no                 yes
    |                   |
testbench noise    localize bottleneck
                    /              \
               command path       data path
                 |                  |
             scheduler/FSM      PHY/timing/noise
                 |                  |
             timing limits      training/calibration

Stop at first failing mechanism, then patch and re-measure.

Review memo template

DRAM REVIEW MEMO - Memory Controller Scheduling / Request Queues, Reorder Windows, and Bank-Level Parallelism

1. Symptom
   - Watched metric: P95/P99 memory access latency versus sustained bandwidth under mixed read/write traffic.
   - Failing traffic slice: <workload/phase/class>
   - First failing transition: <row-hit/row-conflict/turnaround/refresh/training>
   - Revision tags: <firmware/controller/timing/board/package>

2. Mechanism hypothesis
   - Primary mechanism: A modern memory controller decouples ingress order from DRAM command issue order through per-channel request queues, rank/bank tracking, and a bounded reorder window. Incoming transactions are first classified by address mapping (channel, rank, bank-group, bank, row, column) and direction (read/write), then inserted into scheduling structures that preserve correctness constraints such as fences, hazards, and ordering domains while still exposing parallelism. Reordering works by pulling forward requests that target currently available banks or already-open rows, while delaying requests that would immediately cause row conflicts, bus turnarounds, or timing violations. The usable gain depends on queue depth and address entropy: too little depth cannot find parallel work, while too much depth can increase head-of-line latency for unlucky flows and make QoS guarantees harder. Effective scheduling therefore combines bank-state prediction, timing-wheel legality checks, and starvation control so the controller increases throughput without letting tail latency explode.
   - Competing hypotheses: <mapping, scheduling, PHY margin, SI/PI, reliability policy>
   - Missing evidence: <command trace, queue snapshot, lane margins, CE/UE logs>

3. Proposed action
   - Smallest reversible change: <policy/register/firmware/flow>
   - Expected movement: <p99 latency, effective bandwidth, stability>
   - Regression risk: fairness, thermal drift, training robustness, field reliability

4. Signoff
   - Re-run artifact: Scheduler trace report with queue occupancy, bank-state transitions, reorder distance histogram, and latency-percentile breakdown.
   - Required owners: memory controller architect, SoC interconnect owner, performance modeling owner, firmware QoS owner, silicon validation owner
   - Final decision: ship, bounded rollout, rollback, or escalate

DRAM deep dive

Controller policy decides whether DRAM serves locality, fairness, and QoS targets simultaneously.

Concept diagram

CONTROLLER SCHEDULING LOOP

request queues -> row-policy + priority -> command issue -> bank state update

Metric graph

QUEUE PRESSURE MIX

row-hit preference bias ██████
aging/fairness pressure █████
QoS override cost       ███

Reports and artifacts

• scheduler policy comparison

• queue age distribution

• starvation/fairness incident report

• QoS latency percentile dashboard

Mini case study

FR-FCFS tuning improved bulk throughput but starved latency-critical traffic until age caps and class quotas were added.

Debug branches

• Measure queue age tails by traffic class

• Separate row-hit gains from fairness regressions

• Stress policy under mixed burst and random streams

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?

Key takeaways

• Always tie controller and PHY counter shifts to application latency and throughput outcomes.

• Lock firmware timing profile, thermal condition, and DIMM state before comparing DRAM captures.

Common pitfalls

• Chasing peak bandwidth while ignoring p99 latency and fairness tails.

• Changing timing guardbands without separating SI noise from scheduling issues.

• Declaring closure without reliability gates, fault injection, and regression replay.

Principal DRAM review addendum

Request Queues, Reorder Windows, and Bank-Level Parallelism should be read as an end-to-end memory behavior, not as a single block definition. A production DRAM subsystem reflects interactions between array physics, command legality, scheduler policy, PHY margin, and reliability controls before software experiences final latency or bandwidth.

A modern memory controller decouples ingress order from DRAM command issue order through per-channel request queues, rank/bank tracking, and a bounded reorder window. Incoming transactions are first classified by address mapping (channel, rank, bank-group, bank, row, column) and direction (read/write), then inserted into scheduling structures that preserve correctness constraints such as fences, hazards, and ordering domains while still exposing parallelism. Reordering works by pulling forward requests that target currently available banks or already-open rows, while delaying requests that would immediately cause row conflicts, bus turnarounds, or timing violations. The usable gain depends on queue depth and address entropy: too little depth cannot find parallel work, while too much depth can increase head-of-line latency for unlucky flows and make QoS guarantees harder. Effective scheduling therefore combines bank-state prediction, timing-wheel legality checks, and starvation control so the controller increases throughput without letting tail latency explode. DRAM inefficiency is multiplicative: one extra ACTIVATE, one unnecessary turnaround, one weak lane margin, or one refresh collision repeated across billions of accesses can dominate product tail latency and power.

Use P95/P99 memory access latency versus sustained bandwidth under mixed read/write traffic. as the opening signal, not the conclusion. A metric move only becomes actionable when paired with workload context, command traces, training telemetry, and evidence artifacts such as Scheduler trace report with queue occupancy, bank-state transitions, reorder distance histogram, and latency-percentile breakdown..

Memory-controller quality is measured by throughput and tail predictability under mixed traffic, not average bandwidth alone. Senior review quality comes from proving a complete chain: request pattern -> memory-state transition -> bottleneck mechanism -> smallest owner fix -> regression-safe validation.

Review discipline should enforce a single causal chain: traffic pattern -> command-level behavior -> array/PHY effect -> measured product impact. That chain prevents tuning folklore from replacing evidence.