DRAM & Memory Design · All levels
Request Queues, Reorder Windows, and Bank-Level Parallelism: Interview Drills
Interview Drills for Request Queues, Reorder Windows, and Bank-Level Parallelism.
Interview drills
Interview Drills for Request Queues, Reorder Windows, and Bank-Level Parallelism focuses on P95/P99 memory access latency versus sustained bandwidth under mixed read/write traffic.. The purpose is to turn memory observations into mechanism-backed actions with explicit owners and release-safe validation.
PROMPT
You observe P95/P99 memory access latency versus sustained bandwidth under mixed read/write traffic. on Request Queues, Reorder Windows, and Bank-Level Parallelism. Explain root cause and release decision.
STRONG ANSWER
1. Defines failing traffic context and first transition loss.
2. Explains mechanism: A modern memory controller decouples ingress order from DRAM command issue order through per-channel request queues, rank/bank tracking, and a bounded reorder window. Incoming transactions are first classified by address mapping (channel, rank, bank-group, bank, row, column) and direction (read/write), then inserted into scheduling structures that preserve correctness constraints such as fences, hazards, and ordering domains while still exposing parallelism. Reordering works by pulling forward requests that target currently available banks or already-open rows, while delaying requests that would immediately cause row conflicts, bus turnarounds, or timing violations. The usable gain depends on queue depth and address entropy: too little depth cannot find parallel work, while too much depth can increase head-of-line latency for unlucky flows and make QoS guarantees harder. Effective scheduling therefore combines bank-state prediction, timing-wheel legality checks, and starvation control so the controller increases throughput without letting tail latency explode.
3. Requests proving artifact: Scheduler trace report with queue occupancy, bank-state transitions, reorder distance histogram, and latency-percentile breakdown.
4. Proposes bounded fix + owner + rollback-safe validation.
WEAK ANSWER
Gives generic DDR tuning ideas without command evidence, owner accountability, or risk controls.Interview evidence matrix
DRAM EVIDENCE MATRIX - Request Queues, Reorder Windows, and Bank-Level Parallelism
+-------------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence | Tells you | Does not prove | Next action |
+-------------------------------+--------------------------------+--------------------------------+---------------------------+
| row-hit/miss + ACT/PRE mix | locality and row-state cost | lane-level capture integrity | inspect training margins |
| queue age + class breakdown | fairness and starvation risk | command legality details | parse command timeline |
| JEDEC legality + bus timeline | timing-window pressure | root cause by itself | correlate with traffic map|
| eye / Vref / skew snapshots | PHY margin and drift behavior | controller policy quality | pair with schedule logs |
| CE/UE + scrub telemetry | reliability trajectory | immediate perf bottleneck only | map to hotspot addresses |
+-------------------------------+--------------------------------+--------------------------------+---------------------------+DRAM deep dive
Controller policy decides whether DRAM serves locality, fairness, and QoS targets simultaneously.
Concept diagram
CONTROLLER SCHEDULING LOOP
request queues -> row-policy + priority -> command issue -> bank state updateMetric graph
QUEUE PRESSURE MIX
row-hit preference bias ██████
aging/fairness pressure █████
QoS override cost ███Reports and artifacts
scheduler policy comparison
queue age distribution
starvation/fairness incident report
QoS latency percentile dashboard
Mini case study
FR-FCFS tuning improved bulk throughput but starved latency-critical traffic until age caps and class quotas were added.
Debug branches
Measure queue age tails by traffic class
Separate row-hit gains from fairness regressions
Stress policy under mixed burst and random streams
Senior review question
Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?
Key takeaways
Always tie controller and PHY counter shifts to application latency and throughput outcomes.
Lock firmware timing profile, thermal condition, and DIMM state before comparing DRAM captures.
Common pitfalls
Chasing peak bandwidth while ignoring p99 latency and fairness tails.
Changing timing guardbands without separating SI noise from scheduling issues.
Declaring closure without reliability gates, fault injection, and regression replay.
Interview answer expansion
Strong interview answers for Request Queues, Reorder Windows, and Bank-Level Parallelism start with workload framing and metric framing, then explain mechanism plainly: A modern memory controller decouples ingress order from DRAM command issue order through per-channel request queues, rank/bank tracking, and a bounded reorder window. Incoming transactions are first classified by address mapping (channel, rank, bank-group, bank, row, column) and direction (read/write), then inserted into scheduling structures that preserve correctness constraints such as fences, hazards, and ordering domains while still exposing parallelism. Reordering works by pulling forward requests that target currently available banks or already-open rows, while delaying requests that would immediately cause row conflicts, bus turnarounds, or timing violations. The usable gain depends on queue depth and address entropy: too little depth cannot find parallel work, while too much depth can increase head-of-line latency for unlucky flows and make QoS guarantees harder. Effective scheduling therefore combines bank-state prediction, timing-wheel legality checks, and starvation control so the controller increases throughput without letting tail latency explode.
Then propose a measurement plan: command legality, row-hit dynamics, turnaround cost, refresh interference, and PHY margin where relevant.
Finally, present one bounded fix plus regression risk. DRAM interviews reward explicit tradeoff ownership, not generic tuning slogans.