DRAM Fundamentals & Cell Physics

Section goal

Bitcells, capacitors, sense amplifiers, refresh, retention, and the electrical behavior that makes DRAM different from SRAM and logic.

This section trains how to reason from traffic behavior to DRAM mechanism, then close with owner accountability, reliability gates, and release-safe decisions.

How to study this section

1. Start with each topic hub and draw the mechanism path.

2. Use reports and debug pages to prove causality before tuning.

3. Practice worked examples and interview drills with explicit evidence chains.

4. Close each topic with checklist and silicon impact pages.

Topics

1. one-transistor-one-capacitor-cell/ - 1T1C Cell Operation and Charge Storage Limits

2. sense-amplifiers-and-bitlines/ - Sense Amplifiers, Bitline Pairing, and Restore

3. precharge-activate-read-write/ - PRECHARGE -> ACTIVATE -> READ/WRITE Command Physics

4. retention-refresh-and-leakage/ - Retention Tails, Refresh Policy, and Leakage Control

Related topics

• DRAM & Memory Design course hub

DRAM deep dive

DRAM behavior is controlled by row lifecycle economics: activate, sense, restore, and precharge discipline.

Concept diagram

DRAM ACCESS PRIMITIVES

request -> ACT (open row) -> READ/WRITE burst -> PRE (close row)
bank groups + refresh windows bound true throughput

Metric graph

ROW ACCESS MIX

row hits         ███████
row conflicts    █████
row misses       ███

Reports and artifacts

• row-buffer locality profile

• ACT/PRE command balance report

• bank-level parallelism summary

• latency tail sheet

Mini case study

A workload with random page touches collapsed row-hit rate; queue depth looked healthy but effective bandwidth fell 28%.

Debug branches

• Classify latency by row hit, conflict, and miss paths

• Correlate bank-group parallelism with queue drain rate

• Separate refresh-induced stalls from scheduler artifacts

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?