PRECHARGE -> ACTIVATE -> READ/WRITE Command Physics: Debug Playbook

Debug playbook

Debug Playbook for PRECHARGE -> ACTIVATE -> READ/WRITE Command Physics focuses on Timing closure on tRP, tRCD, CL/CWL, tWR, and tRAS under worst-case RC.. The purpose is to turn memory observations into mechanism-backed actions with explicit owners and release-safe validation.

DRAM debug should narrow from broad symptom to one dominant mechanism. Avoid mixed-knob sweeps that produce accidental wins without causal confidence.

1. Freeze workload seed, firmware image, timing profile, and thermal setup.

2. Find first failing transition in command timeline.

3. Classify mechanism: locality loss, legality pressure, queue policy, margin drift, or RAS behavior.

4. Build focused reproducer for top hypothesis.

5. Apply minimal reversible fix and define rollback gate.

6. Re-run full performance + reliability matrix.

Debug decision tree

ROOT CAUSE TREE - PRECHARGE -> ACTIVATE -> READ/WRITE Command Physics

Timing closure on tRP, tRCD, CL/CWL, tWR, and tRAS under worst-case RC. regressed
        |
reproducible with fixed seed?
      /               \
    no                 yes
    |                   |
testbench noise    localize bottleneck
                    /              \
               command path       data path
                 |                  |
             scheduler/FSM      PHY/timing/noise
                 |                  |
             timing limits      training/calibration

Stop at first failing mechanism, then patch and re-measure.

Review memo template

DRAM REVIEW MEMO - DRAM Fundamentals & Cell Physics / PRECHARGE -> ACTIVATE -> READ/WRITE Command Physics

1. Symptom
   - Watched metric: Timing closure on tRP, tRCD, CL/CWL, tWR, and tRAS under worst-case RC.
   - Failing traffic slice: <workload/phase/class>
   - First failing transition: <row-hit/row-conflict/turnaround/refresh/training>
   - Revision tags: <firmware/controller/timing/board/package>

2. Mechanism hypothesis
   - Primary mechanism: PRECHARGE equalizes complementary bitlines to a reference (commonly VDD/2) and disconnects sensing paths so the next row starts from known initial conditions. ACTIVATE raises one wordline, coupling selected cells to their columns and initiating charge sharing; only after sufficient differential develops can READ latch data from the sensing path. WRITE drives the resolved bitline state strongly while wordline is high to overwrite cell charge, then requires write recovery before precharge to guarantee full capacitor programming. Command legality constraints arise from analog settling, not protocol arbitrariness: precharging too early truncates restore, activating too soon after precharge leaves residual imbalance, and back-to-back row operations are bounded by shared array power rails and local wordline driver recovery.
   - Competing hypotheses: <mapping, scheduling, PHY margin, SI/PI, reliability policy>
   - Missing evidence: <command trace, queue snapshot, lane margins, CE/UE logs>

3. Proposed action
   - Smallest reversible change: <policy/register/firmware/flow>
   - Expected movement: <p99 latency, effective bandwidth, stability>
   - Regression risk: fairness, thermal drift, training robustness, field reliability

4. Signoff
   - Re-run artifact: Per-subarray timing dependency map linking JEDEC timings to internal analog events.
   - Required owners: DRAM architect, circuit designer, memory controller owner, validation owner, product reliability owner
   - Final decision: ship, bounded rollout, rollback, or escalate

DRAM deep dive

DRAM behavior is controlled by row lifecycle economics: activate, sense, restore, and precharge discipline.

Concept diagram

DRAM ACCESS PRIMITIVES

request -> ACT (open row) -> READ/WRITE burst -> PRE (close row)
bank groups + refresh windows bound true throughput

Metric graph

ROW ACCESS MIX

row hits         ███████
row conflicts    █████
row misses       ███

Reports and artifacts

• row-buffer locality profile

• ACT/PRE command balance report

• bank-level parallelism summary

• latency tail sheet

Mini case study

A workload with random page touches collapsed row-hit rate; queue depth looked healthy but effective bandwidth fell 28%.

Debug branches

• Classify latency by row hit, conflict, and miss paths

• Correlate bank-group parallelism with queue drain rate

• Separate refresh-induced stalls from scheduler artifacts

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?

Key takeaways

• Always tie controller and PHY counter shifts to application latency and throughput outcomes.

• Lock firmware timing profile, thermal condition, and DIMM state before comparing DRAM captures.

Common pitfalls

• Chasing peak bandwidth while ignoring p99 latency and fairness tails.

• Changing timing guardbands without separating SI noise from scheduling issues.

• Declaring closure without reliability gates, fault injection, and regression replay.

Principal DRAM review addendum

PRECHARGE -> ACTIVATE -> READ/WRITE Command Physics should be read as an end-to-end memory behavior, not as a single block definition. A production DRAM subsystem reflects interactions between array physics, command legality, scheduler policy, PHY margin, and reliability controls before software experiences final latency or bandwidth.

PRECHARGE equalizes complementary bitlines to a reference (commonly VDD/2) and disconnects sensing paths so the next row starts from known initial conditions. ACTIVATE raises one wordline, coupling selected cells to their columns and initiating charge sharing; only after sufficient differential develops can READ latch data from the sensing path. WRITE drives the resolved bitline state strongly while wordline is high to overwrite cell charge, then requires write recovery before precharge to guarantee full capacitor programming. Command legality constraints arise from analog settling, not protocol arbitrariness: precharging too early truncates restore, activating too soon after precharge leaves residual imbalance, and back-to-back row operations are bounded by shared array power rails and local wordline driver recovery. DRAM inefficiency is multiplicative: one extra ACTIVATE, one unnecessary turnaround, one weak lane margin, or one refresh collision repeated across billions of accesses can dominate product tail latency and power.

Use Timing closure on tRP, tRCD, CL/CWL, tWR, and tRAS under worst-case RC. as the opening signal, not the conclusion. A metric move only becomes actionable when paired with workload context, command traces, training telemetry, and evidence artifacts such as Per-subarray timing dependency map linking JEDEC timings to internal analog events..

DRAM fundamentals are analog-first limits that digital protocol must respect, not optional implementation detail. Senior review quality comes from proving a complete chain: request pattern -> memory-state transition -> bottleneck mechanism -> smallest owner fix -> regression-safe validation.

Review discipline should enforce a single causal chain: traffic pattern -> command-level behavior -> array/PHY effect -> measured product impact. That chain prevents tuning folklore from replacing evidence.