DRAM & Memory Design · All levels
DRAM Glossary
Shared vocabulary across DRAM architecture, controller policy, PHY training, and RAS.
Terms to use precisely
Row hit: request served from currently open row with minimal activate overhead.
Row conflict: desired row differs from open row, requiring precharge/activate sequence.
Turnaround: dead cycles incurred when switching command or bus direction.
tFAW: four-activate rolling window limit tied to power integrity constraints.
Write leveling/read training: calibrations aligning DQ and DQS timing windows.
TRR: target-row refresh style mitigation for rowhammer-like disturbance.