DRAM & Memory Design · All levels

Patrol Scrub and RAS Policy: Interview Drills

Interview Drills for Patrol Scrub and RAS Policy.

Interview drills

Interview Drills for Patrol Scrub and RAS Policy focuses on scrub interval coverage, latent fault dwell time, corrected-before-failure ratio. The purpose is to turn memory observations into mechanism-backed actions with explicit owners and release-safe validation.

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PROMPT
You observe scrub interval coverage, latent fault dwell time, corrected-before-failure ratio on Patrol Scrub and RAS Policy. Explain root cause and release decision.

STRONG ANSWER
1. Defines failing traffic context and first transition loss.
2. Explains mechanism: Patrol scrub proactively reads and rewrites DRAM lines so single-bit faults are corrected before accumulating into multi-bit uncorrectable events; RAS policy balances scrub aggressiveness against bandwidth and power overhead.
3. Requests proving artifact: scrub scheduler log, CE aging report, patrol coverage audit
4. Proposes bounded fix + owner + rollback-safe validation.

WEAK ANSWER
Gives generic DDR tuning ideas without command evidence, owner accountability, or risk controls.

Interview evidence matrix

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DRAM EVIDENCE MATRIX - Patrol Scrub and RAS Policy

+-------------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence                      | Tells you                      | Does not prove                 | Next action               |
+-------------------------------+--------------------------------+--------------------------------+---------------------------+
| row-hit/miss + ACT/PRE mix    | locality and row-state cost    | lane-level capture integrity   | inspect training margins  |
| queue age + class breakdown   | fairness and starvation risk   | command legality details       | parse command timeline    |
| JEDEC legality + bus timeline | timing-window pressure         | root cause by itself           | correlate with traffic map|
| eye / Vref / skew snapshots   | PHY margin and drift behavior  | controller policy quality      | pair with schedule logs   |
| CE/UE + scrub telemetry       | reliability trajectory         | immediate perf bottleneck only | map to hotspot addresses  |
+-------------------------------+--------------------------------+--------------------------------+---------------------------+

DRAM deep dive

Reliability closure combines ECC policy, scrub cadence, and disturbance mitigation like row-hammer controls.

Concept diagram

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RELIABILITY LOOP

error detect -> ECC correct/report -> scrub/retire policy -> monitor recurrence

Metric graph

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ERROR MANAGEMENT TREND

correctable events    ███████
silent-data-risk      ██
unrecoverable events  █

Reports and artifacts

correctable/uncorrectable error trend
scrub interval effectiveness report
row-hammer monitor log
fault-injection coverage summary

Mini case study

Relaxed scrub interval improved bandwidth in test but allowed burst correctables to cluster into service-visible latency spikes.

Debug branches

Segment ECC events by bank, rank, and temperature
Tune scrub cadence with workload-aware idle windows
Verify row-hammer mitigation using adversarial patterns

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?

Key takeaways

Always tie controller and PHY counter shifts to application latency and throughput outcomes.
Lock firmware timing profile, thermal condition, and DIMM state before comparing DRAM captures.

Common pitfalls

Chasing peak bandwidth while ignoring p99 latency and fairness tails.
Changing timing guardbands without separating SI noise from scheduling issues.
Declaring closure without reliability gates, fault injection, and regression replay.

Interview answer expansion

Strong interview answers for Patrol Scrub and RAS Policy start with workload framing and metric framing, then explain mechanism plainly: Patrol scrub proactively reads and rewrites DRAM lines so single-bit faults are corrected before accumulating into multi-bit uncorrectable events; RAS policy balances scrub aggressiveness against bandwidth and power overhead.

Then propose a measurement plan: command legality, row-hit dynamics, turnaround cost, refresh interference, and PHY margin where relevant.

Finally, present one bounded fix plus regression risk. DRAM interviews reward explicit tradeoff ownership, not generic tuning slogans.

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