DRAM & Memory Design · All levels
Patrol Scrub and RAS Policy: Pitfalls and Red Flags
Pitfalls and Red Flags for Patrol Scrub and RAS Policy.
Pitfalls and red flags
Pitfalls and Red Flags for Patrol Scrub and RAS Policy focuses on scrub interval coverage, latent fault dwell time, corrected-before-failure ratio. The purpose is to turn memory observations into mechanism-backed actions with explicit owners and release-safe validation.
Using average throughput as closure while latency tails remain unstable.
Assuming training PASS at one corner implies production robustness.
Changing timing guardbands without SI/PI and thermal correlation.
Ignoring fairness regressions while improving row-hit preference.
Skipping reliability impact checks for performance policy updates.
DRAM deep dive
Reliability closure combines ECC policy, scrub cadence, and disturbance mitigation like row-hammer controls.
Concept diagram
RELIABILITY LOOP
error detect -> ECC correct/report -> scrub/retire policy -> monitor recurrenceMetric graph
ERROR MANAGEMENT TREND
correctable events ███████
silent-data-risk ██
unrecoverable events █Reports and artifacts
correctable/uncorrectable error trend
scrub interval effectiveness report
row-hammer monitor log
fault-injection coverage summary
Mini case study
Relaxed scrub interval improved bandwidth in test but allowed burst correctables to cluster into service-visible latency spikes.
Debug branches
Segment ECC events by bank, rank, and temperature
Tune scrub cadence with workload-aware idle windows
Verify row-hammer mitigation using adversarial patterns
Senior review question
Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?
Key takeaways
Always tie controller and PHY counter shifts to application latency and throughput outcomes.
Lock firmware timing profile, thermal condition, and DIMM state before comparing DRAM captures.
Common pitfalls
Chasing peak bandwidth while ignoring p99 latency and fairness tails.
Changing timing guardbands without separating SI noise from scheduling issues.
Declaring closure without reliability gates, fault injection, and regression replay.
Why common mistakes happen
Memory teams often over-trust aggregate counters. Bus utilization, row-hit rate, and throughput are useful but each can hide severe tail-latency or reliability risk.
Another trap is lab overfitting. A fix can pass synthetic traffic yet fail mixed real workloads because command interleaving and class contention differ.
Senior review asks what evidence could falsify the current claim. If no disconfirming trace or corner test exists, the root-cause narrative is still weak.