DRAM & Memory Design · All levels

Rowhammer and Disturb Effects: Review Checklist

Review Checklist for Rowhammer and Disturb Effects.

Review checklist

Review Checklist for Rowhammer and Disturb Effects focuses on hammer threshold margin, disturb-induced bit flip count, mitigation hit rate. The purpose is to turn memory observations into mechanism-backed actions with explicit owners and release-safe validation.

  • Workload scope and SLA targets are explicit.

  • Environment tags are locked and reproducible.

  • First failing transition is proven by command-level evidence.

  • Owner and rollback criteria are documented.

  • Validation matrix covers performance, stability, and reliability.

  • Owners signed: memory controller owner, security architect, validation owner.

DRAM deep dive

Reliability closure combines ECC policy, scrub cadence, and disturbance mitigation like row-hammer controls.

Concept diagram

diagram
RELIABILITY LOOP

error detect -> ECC correct/report -> scrub/retire policy -> monitor recurrence

Metric graph

diagram
ERROR MANAGEMENT TREND

correctable events    ███████
silent-data-risk      ██
unrecoverable events  █

Reports and artifacts

  • correctable/uncorrectable error trend

  • scrub interval effectiveness report

  • row-hammer monitor log

  • fault-injection coverage summary

Mini case study

Relaxed scrub interval improved bandwidth in test but allowed burst correctables to cluster into service-visible latency spikes.

Debug branches

  • Segment ECC events by bank, rank, and temperature

  • Tune scrub cadence with workload-aware idle windows

  • Verify row-hammer mitigation using adversarial patterns

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?

Key takeaways

  • Always tie controller and PHY counter shifts to application latency and throughput outcomes.

  • Lock firmware timing profile, thermal condition, and DIMM state before comparing DRAM captures.

Common pitfalls

  • Chasing peak bandwidth while ignoring p99 latency and fairness tails.

  • Changing timing guardbands without separating SI noise from scheduling issues.

  • Declaring closure without reliability gates, fault injection, and regression replay.

Review checklist explanation

A checklist here protects against false closure. Every item should map to a known memory failure mode.

For Rowhammer and Disturb Effects, minimum checklist: workload scope, hammer threshold margin, disturb-induced bit flip count, mitigation hit rate, artifact evidence (rowhammer stress log, aggressor-victim address trace, mitigation counter report), bottleneck class, owner, rollback path, and corner-matrix validation.

If controller or firmware changed, include fairness and RAS checks. If PHY or package assumptions changed, include SI/PI and thermal guardband evidence.